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"Design of Error-Resilient Logic Gates with Reinforcement Using Implications."

Xijing Han et al. (2016)

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DOI: 10.1145/2902961.2902983

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

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  dblp key:
  - conf/glvlsi/HanDBZP16
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  - https://dblp.org/rec/conf/glvlsi/HanDBZP16
Xijing Han, Marco Donato, R. Iris Bahar, Alexander Zaslavsky, William R. Patterson:
Design of Error-Resilient Logic Gates with Reinforcement Using Implications. ACM Great Lakes Symposium on VLSI 2016: 191-196

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