More Web Proxy on the site http://driver.im/

default search action

combined dblp search
author search
venue search
publication search

ask others

"Performance and Area Modeling of Cmplete FPGA Designs in the Presence of ..."

K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz (2003)

> Home

Details and statistics

DOI: 10.1007/978-3-540-45234-8_31

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpl/ShayeePD03
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/ShayeePD03
K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz:
Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. FPL 2003: 313-323

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.