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"Implementation of a Successive Erasure BCH(16, 7, 6) Decoder and ..."

Thomas Buerner (2002)

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DOI: 10.1007/3-540-46117-5_49

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Thomas Buerner:
Implementation of a Successive Erasure BCH(16, 7, 6) Decoder and Performance Simulation by Rapid Prototyping. FPL 2002: 462-471

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