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"Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A ..."

Sameh W. Asaad, Kevin W. Warren (1998)

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DOI: 10.1007/BFB0055255

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Sameh W. Asaad, Kevin W. Warren:
Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience. FPL 1998: 278-287

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