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"Architecture level TSV count minimization methodology for 3D tree-based FPGA."

Vinod Pangracious, Habib Mehrez, Zied Marrakchi (2013)

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DOI: 10.1109/COOLCHIPS.2013.6547925

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/coolchips/PangraciousMM13
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  persistent URL:
  - https://dblp.org/rec/conf/coolchips/PangraciousMM13
Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
Architecture level TSV count minimization methodology for 3D tree-based FPGA. COOL Chips 2013: 1-3

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