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"A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay."

Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu (2002)

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DOI: 10.1109/CICC.2002.1012764

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-04

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Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu:
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay. CICC 2002: 49-52

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