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"Modular model checking of VLSI designs described in VHDL."

Fahim Rahim-Sarwary et al. (1998)

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DOI: —

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type: Conference or Workshop Paper

metadata version: 2021-08-09

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  dblp key:
  - conf/cata/Rahim-SarwaryEMB98
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  persistent URL:
  - https://dblp.org/rec/conf/cata/Rahim-SarwaryEMB98
Fahim Rahim-Sarwary, Emmanuelle Encrenaz, Michel Minoux, Rajesh K. Bawa:
Modular model checking of VLSI designs described in VHDL. CATA 1998: 368-371

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