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Peter-Michael Seidel
Person information
- affiliation: University of Hawaii at Manoa, Honolulu, HI, USA
- affiliation: Southern Methodist University, Dallas, Texas, USA
- affiliation: Saarland University, Saarbrücken, Germany
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2010 – 2019
- 2019
- [c30]Jason Castiglione, Dusko Pavlovic, Peter-Michael Seidel:
Privacy Protocols. Foundations of Security, Protocols, and Equational Reasoning 2019: 167-191 - [i2]Jason Castiglione, Dusko Pavlovic, Peter-Michael Seidel:
Privacy protocols. CoRR abs/1904.05540 (2019) - 2018
- [c29]Peter-Michael Seidel:
High-Performance Multiplication Modulo 2n - 3. ACSSC 2018: 130-134 - [c28]Peter-Michael Seidel:
Variable Latency Division. MWSCAS 2018: 944-947 - 2017
- [c27]Dusko Pavlovic, Peter-Michael Seidel:
Quotients in monadic programming: Projective algebras are equivalent to coalgebras. LICS 2017: 1-12 - [c26]Mark Nelson, Peter-Michael Seidel:
Modeling and Analysis of Secure Processor Extensions Based on Actor Networks. MTV 2017: 68-73 - [i1]Dusko Pavlovic, Peter-Michael Seidel:
Quotients in monadic programming: Projective algebras are equivalent to coalgebras. CoRR abs/1701.07601 (2017) - 2016
- [c25]Dusko Pavlovic, Peter-Michael Seidel:
(Modular) Effect Algebras are Equivalent to (Frobenius) Antispecial Algebras. QPL 2016: 145-160 - 2015
- [c24]Peter-Michael Seidel:
A parametric error analysis of Goldschmidt's square-root algorithm. ACSSC 2015: 727-731 - [c23]Mark Nelson, Peter-Michael Seidel:
Modeling and Analysis of Trusted Boot Processes Based on Actor Network Procedures. MTV 2015: 54-59 - 2014
- [j8]Alberto Nannarelli, Peter-Michael Seidel, Ping Tak Peter Tang:
Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 63(8): 1852-1853 (2014) - [c22]Peter-Michael Seidel:
Directed Test Case Generation for x86 Instruction Decoding. MTV 2014: 78-82 - [c21]Peter-Michael Seidel:
A Case for Multi-level Combination of Theorem Proving and Model Checking Tools. MTV 2014: 90-97 - 2013
- [c20]Jeff Rupley, John King, Eric Quinnell, Frank Galloway, Ken Patton, Peter-Michael Seidel, James Dinh, Hai Bui, Anasua Bhowmik:
The Floating-Point Unit of the Jaguar x86 Core. IEEE Symposium on Computer Arithmetic 2013: 7-16 - [e1]Alberto Nannarelli, Peter-Michael Seidel, Ping Tak Peter Tang:
21st IEEE Symposium on Computer Arithmetic, ARITH 2013, Austin, TX, USA, April 7-10, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-5644-2 [contents] - 2011
- [c19]Peter-Michael Seidel:
Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback. ACL2 2011: 70-83 - 2010
- [c18]Peter-Michael Seidel, Georgi Gaydadjiev, Sofiène Tahar, Lars J. Svensson:
Welcome to ICCD 2010! ICCD 2010
2000 – 2009
- 2007
- [c17]Nikhil Kikkeri, Peter-Michael Seidel:
An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder. ASAP 2007: 83-88 - [c16]Ronen Goldberg, Guy Even, Peter-Michael Seidel:
An FPGA implementation of pipelined multiplicative division with IEEE Rounding. FCCM 2007: 185-196 - 2006
- [c15]Nikhil Kikkeri, Peter-Michael Seidel:
Optimized Arithmetic Hardware Design based on Hierarchical Formal Verification. ICECS 2006: 541-544 - 2005
- [j7]Guy Even, Peter-Michael Seidel, Warren E. Ferguson:
A parametric error analysis of Goldschmidt's division algorithm. J. Comput. Syst. Sci. 70(1): 118-139 (2005) - [j6]Peter-Michael Seidel, Lee D. McFearin, David W. Matula:
Secondary Radix Recodings for Higher Radix Multipliers. IEEE Trans. Computers 54(2): 111-123 (2005) - [c14]Peter-Michael Seidel:
High-Radix Implementation of IEEE Floating-Point Addition. IEEE Symposium on Computer Arithmetic 2005: 99-106 - [c13]Nikhil Kikkeri, Peter-Michael Seidel:
Formal Verification of Parametric Multiplicative Division Implementations. ICCD 2005: 599-602 - [c12]Nathaniel Ayewah, Nikhil Kikkeri, Peter-Michael Seidel:
Challenges in the Formal Verification of Complete State-of-the-Art Processors. ICCD 2005: 603-608 - 2004
- [j5]Peter-Michael Seidel, Guy Even:
Delay-Optimized Implementation of IEEE Floating-Point Addition. IEEE Trans. Computers 53(2): 97-113 (2004) - [c11]Steven D. Krueger, Peter-Michael Seidel:
Design of an On-Line IEEE Floating-Point Addition Unit for FPGAs. FCCM 2004: 239-246 - [c10]Nikhil Kikkeri, Peter-Michael Seidel:
Formal Hardware Verification based on Signal Correlation Properties. ICCD 2004: 402-408 - [c9]Peter-Michael Seidel, Kenneth Fazel:
Two-Dimensional Folding Strategies for Improved Layouts of Cyclic Shifters. ISVLSI 2004: 277-278 - 2003
- [c8]Guy Even, Peter-Michael Seidel, Warren E. Ferguson:
A Parametric Error Analysis of Goldschmidt?s Division Algorithm. IEEE Symposium on Computer Arithmetic 2003: 165- - [c7]Guy Even, Peter-Michael Seidel:
Pipelined Multiplicative Division with IEEE Rounding. ICCD 2003: 240- - 2002
- [j4]Wolfgang J. Paul, Peter-Michael Seidel:
To Booth or not to Booth. Integr. 32(1-2): 5-40 (2002) - 2001
- [c6]Peter-Michael Seidel, Lee D. McFearin, David W. Matula:
Binary Multiplication Radix-32 and Radix-256. IEEE Symposium on Computer Arithmetic 2001: 23-32 - [c5]Peter-Michael Seidel, Guy Even:
On the Design of Fast IEEE Floating-Point Adders. IEEE Symposium on Computer Arithmetic 2001: 184-194 - [c4]Mark A. Hillebrand, Thomas Schurger, Peter-Michael Seidel:
How to Half Wire Lengths in the Layout of Cyclic Shifter. VLSI Design 2001: 339-344 - 2000
- [j3]Guy Even, Silvia M. Müller, Peter-Michael Seidel:
A dual precision IEEE floating-point multiplier. Integr. 29(2): 167-180 (2000) - [j2]Guy Even, Peter-Michael Seidel:
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication. IEEE Trans. Computers 49(7): 638-650 (2000)
1990 – 1999
- 1999
- [b1]Peter-Michael Seidel:
On the design of IEEE compliant floating point units and their quantitative analysis. Saarland University, Saarbrücken, Germany, 1999, pp. 1-188 - [j1]Peter-Michael Seidel:
High-speed redundant reciprocal approximation. Integr. 28(1): 1-12 (1999) - [c3]Guy Even, Peter-Michael Seidel:
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication. IEEE Symposium on Computer Arithmetic 1999: 225-232 - 1998
- [c2]Peter-Michael Seidel:
How to Half the Latency of IEEE Compliant Floating-Point Multiplication. EUROMICRO 1998: 10329-10332 - [c1]Peter-Michael Seidel, Guy Even:
How many logic levels does floating-point addition require? ICCD 1998: 142-149
Coauthor Index
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