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Daniel A. Jiménez
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- affiliation: Texas A&M University, College Station, TX, USA
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2020 – today
- 2024
- [c68]Alexandre Valentin Jamet, Georgios Vavouliotis, Daniel A. Jiménez, Lluc Alvarez, Marc Casas:
A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering. HPCA 2024: 528-542 - [c67]Alexandre Valentin Jamet, Georgios Vavouliotis, Daniel A. Jiménez, Lluc Alvarez, Marc Casas:
Practically Tackling Memory Bottlenecks of Graph-Processing Workloads. IPDPS 2024: 1034-1045 - [c66]Daniel A. Jiménez, Alaa R. Alameldeen:
Message from the MICRO 2024 Program Chairs. MICRO 2024: xxvi-xxvii - [i5]Alexandre Valentin Jamet, Georgios Vavouliotis, Daniel A. Jiménez, Lluc Alvarez, Marc Casas:
A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering. CoRR abs/2403.15181 (2024) - [i4]Bhargav Reddy Godala, Sankara Prasad Ramesh, Krishnam Tibrewala, Chrysanthos Pepi, Gino Chacon, Svilen Kanev, Gilles A. Pokam, Daniel A. Jiménez, Paul V. Gratz, David I. August:
Correct Wrong Path. CoRR abs/2408.05912 (2024) - [i3]Chrysanthos Pepi, Bhargav Reddy Godala, Krishnam Tibrewala, Gino Chacon, Paul V. Gratz, Daniel A. Jiménez, Gilles A. Pokam, David I. August:
Exposing Shadow Branches. CoRR abs/2408.12592 (2024) - 2023
- [j18]Daniel A. Jiménez
, Elvira Teran
Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching. IEEE Comput. Archit. Lett. 22(1): 17-20 (2023) - [c65]Josué Feliu
Rebasing Microarchitectural Research with Industry Traces. IISWC 2023: 100-114 - [c64]Gino Chacon, Nathan Gober, Krishnendra Nathella, Paul V. Gratz, Daniel A. Jiménez:
A Characterization of the Effects of Software Instruction Prefetching on an Aggressive Front-end. ISPASS 2023: 61-70 - 2022
- [c63]Laith M. AlBarakat, Paul V. Gratz
SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches. ICCD 2022: 50-58 - [c62]Gino Chacon, Elba Garza, Alexandra Jimborean, Alberto Ros
Composite Instruction Prefetching. ICCD 2022: 471-478 - [c61]Shixin Song, Tanvir Ahmed Khan
Thermometer: profile-guided btb replacement for data center applications. ISCA 2022: 742-756 - [c60]Tanvir Ahmed Khan
Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications. MICRO 2022: 19-34 - [c59]Georgios Vavouliotis
Page Size Aware Cache Prefetching. MICRO 2022: 956-974 - [c58]Brady Testa, Samira Mirbagher Ajorpaz
Dynamic Set Stealing to Improve Cache Performance. SBAC-PAD 2022: 60-70 - [i2]Nathan Gober, Gino Chacon, Lei Wang
The Championship Simulator: Architectural Simulation for Education and Competition. CoRR abs/2210.14324 (2022) - 2021
- [j17]Daniel A. Jiménez:
Top Picks From the 2020 Computer Architecture Conferences. IEEE Micro 41(3): 6-9 (2021) - [c57]Georgios Vavouliotis
Exploiting Page Table Locality for Agile TLB Prefetching. ISCA 2021: 85-98 - [c56]Georgios Vavouliotis
Morrigan: A Composite Instruction TLB Prefetcher. MICRO 2021: 1138-1153 - 2020
- [c55]Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. DATE 2020: 169-174 - [c54]Laith M. AlBarakat, Paul V. Gratz
SB-Fetch: synchronization aware hardware prefetching for chip multiprocessors. ICS 2020: 15:1-15:12 - [c53]Alexandre Valentin Jamet
Characterizing the impact of last-level cache replacement policies on big-data workloads. IISWC 2020: 134-144 - [c52]Brian Grayson, Jeff Rupley, Gerald D. Zuraski, Eric Quinnell, Daniel A. Jiménez
Evolution of the Samsung Exynos CPU Microarchitecture. ISCA 2020: 40-51 - [c51]Daniel A. Jiménez:
Support for Diverse Students. KDD 2020: 3584 - [c50]Samira Mirbagher Ajorpaz
CHiRP: Control-Flow History Reuse Prediction. MICRO 2020: 131-145 - [c49]Samira Mirbagher Ajorpaz
PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron. MICRO 2020: 1124-1137
2010 – 2019
- 2019
- [c48]Eshan Bhatia, Gino Chacon, Seth H. Pugsley, Elvira Teran, Paul V. Gratz
Perceptron-based prefetch filtering. ISCA 2019: 1-13 - [c47]Elba Garza, Samira Mirbagher Ajorpaz
Bit-level perceptron prediction for indirect branches. ISCA 2019: 27-38 - [c46]Luna Backes, Daniel A. Jiménez
The impact of cache inclusion policies on cache management techniques. MEMSYS 2019: 428-438 - [i1]Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, S. Nabavi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Daniel Ödman, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, Kevin Mika, A. Hüffmeier, Th. Jungeblu, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber:
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. CoRR abs/1912.01563 (2019) - 2018
- [j16]Laith M. AlBarakat
MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors. IEEE Comput. Archit. Lett. 17(2): 175-178 (2018) - [c45]Elvira Teran
Flexible associativity for DRAM caches. CF 2018: 88-96 - [c44]Samira Mirbagher Ajorpaz
Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer. ISCA 2018: 519-532 - 2017
- [c43]Jinchun Kim, Elvira Teran
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy. ASPLOS 2017: 737-749 - [c42]Daniel A. Jiménez
Multiperspective reuse prediction. MICRO 2017: 436-448 - 2016
- [j15]Qixiao Liu
Sensible Energy Accounting with Abstract Metering for Multicore Systems. ACM Trans. Archit. Code Optim. 12(4): 60:1-60:26 (2016) - [c41]Elvira Teran
Minimal disturbance placement and promotion. HPCA 2016: 201-211 - [c40]Elvira Teran
Perceptron learning for reuse prediction. MICRO 2016: 2:1-2:12 - [c39]Zhe Wang, Daniel A. Jiménez
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor. SBAC-PAD 2016: 109-117 - 2015
- [c38]Yingying Tian, Sooraj Puthoor, Joseph L. Greathouse, Bradford M. Beckmann, Daniel A. Jiménez
Adaptive GPU cache bypassing. GPGPU@PPoPP 2015: 25-35 - 2014
- [j14]Hyungjun Kim, Boris Grot
Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip. IEEE Trans. Computers 63(3): 543-556 (2014) - [c37]Zhe Wang, Daniel A. Jiménez
Adaptive placement and migration policy for an STT-RAM-based hybrid cache. HPCA 2014: 13-24 - [c36]Samira Manabi Khan, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu, Daniel A. Jiménez
Improving cache performance using read-write partitioning. HPCA 2014: 452-463 - [c35]Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez
Last-level cache deduplication. ICS 2014: 53-62 - [c34]David Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul Gratz
B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors. MICRO 2014: 623-634 - 2013
- [j13]Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez
Temporal-based multilevel correlating inclusive cache replacement. ACM Trans. Archit. Code Optim. 10(4): 33:1-33:24 (2013) - [j12]Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Shuai Mu, Yuan Xie, Daniel A. Jiménez
WADE: Writeback-aware dynamic cache management for NVM-based main memory system. ACM Trans. Archit. Code Optim. 10(4): 51:1-51:21 (2013) - [c33]Samira Manabi Khan, Alaa R. Alameldeen, Chris Wilkerson, Jaydeep Kulkarni, Daniel A. Jiménez
Improving multi-core performance using mixed-cell cache architecture. HPCA 2013: 119-130 - [c32]Daniel A. Jiménez
Insertion and promotion for tree-based PseudoLRU last-level caches. MICRO 2013: 284-296 - 2012
- [j11]Reena Panda, Paul V. Gratz
B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors. IEEE Comput. Archit. Lett. 11(2): 41-44 (2012) - [c31]Samira Manabi Khan, Zhe Wang, Daniel A. Jiménez:
Decoupled dynamic cache segmentation. HPCA 2012: 235-246 - [c30]Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez:
Improving writeback efficiency with decoupled last-write prediction. ISCA 2012: 309-320 - [c29]Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez:
Rank idle time prediction driven last-level cache writeback. MSPC 2012: 21-29 - 2011
- [c28]Zhe Wang, Daniel A. Jiménez:
Program Interferometry. PACT 2011: 185-186 - [c27]Yingying Tian, Daniel A. Jiménez
Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy. PACT 2011: 209 - [c26]Zhe Wang, Daniel A. Jiménez:
Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback. PACT 2011: 210 - [c25]Samira Manabi Khan, Daniel A. Jiménez:
Decoupled Cache Segmentation: Mutable Policy with Automated Bypass. PACT 2011: 212 - [c24]Daniel A. Jiménez:
An optimized scaled neural branch predictor. ICCD 2011: 113-118 - [c23]Zhe Wang, Daniel A. Jiménez:
Program Interferometry. IISWC 2011: 172-175 - [c22]Hyungjun Kim, Pritha Ghoshal, Boris Grot
Reducing network-on-chip energy consumption through spatial locality speculation. NOCS 2011: 233-240 - 2010
- [c21]Samira Manabi Khan, Daniel A. Jiménez, Doug Burger, Babak Falsafi:
Using dead blocks as a virtual victim cache. PACT 2010: 489-500 - [c20]Samira Manabi Khan, Daniel A. Jiménez:
Insertion policy selection using Decision Tree Analysis. ICCD 2010: 106-111 - [c19]Samira Manabi Khan, Yingying Tian, Daniel A. Jiménez:
Sampling Dead Block Prediction for Last-Level Caches. MICRO 2010: 175-186
2000 – 2009
- 2009
- [j10]Renée St. Amant, Daniel A. Jiménez, Doug Burger:
Mixed-Signal Approximate Computation: A Neural Predictor Case Study. IEEE Micro 29(1): 104-115 (2009) - [j9]Daniel A. Jiménez:
Generalizing neural branch prediction. ACM Trans. Archit. Code Optim. 5(4): 17:1-17:27 (2009) - [j8]Chunling Hu, Daniel A. Jiménez, Ulrich Kremer:
Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization. Trans. High Perform. Embed. Archit. Compil. 2: 85-104 (2009) - [c18]Daniel A. Jiménez:
Composite Confidence Estimators for Enhanced Speculation Control. SBAC-PAD 2009: 161-168 - 2008
- [j7]Gabriel H. Loh, Daniel A. Jiménez:
Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors. Int. J. Parallel Program. 36(2): 267-286 (2008) - [c17]Miquel Pericàs, Adrián Cristal
A Two-Level Load/Store Queue Based on Execution Locality. ISCA 2008: 25-36 - [c16]Renée St. Amant, Daniel A. Jiménez, Doug Burger:
Low-power, high-performance analog neural branch prediction. MICRO 2008: 447-458 - 2007
- [j6]Chunling Hu, Daniel A. Jiménez
An evaluation infrastructure for power and energy optimisations. Int. J. Embed. Syst. 3(1/2): 31-42 (2007) - [j5]Daniel A. Jiménez:
Guest Editor's Introduction. J. Instr. Level Parallelism 9 (2007) - [c15]Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Daniel A. Jiménez, Mateo Valero:
A Flexible Heterogeneous Multi-Core Architecture. PACT 2007: 13-24 - [c14]Chunling Hu, Daniel A. Jiménez, Ulrich Kremer:
Efficient Program Power Behavior Characterization. HiPEAC 2007: 183-197 - 2006
- [c13]Miquel Pericàs, Adrián Cristal
A decoupled KILO-instruction processor. HPCA 2006: 53-64 - [c12]Daniel A. Jiménez, Gabriel H. Loh:
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. SBAC-PAD 2006: 55-62 - 2005
- [j4]Daniel A. Jiménez:
Idealized Piecewise Linear Branch Prediction. J. Instr. Level Parallelism 7 (2005) - [j3]Chunling Hu, John B. P. McCabe, Daniel A. Jiménez, Ulrich Kremer:
The Camino Compiler infrastructure. SIGARCH Comput. Archit. News 33(5): 3-8 (2005) - [j2]Daniel A. Jiménez:
Improved latency and accuracy for neural branch prediction. ACM Trans. Comput. Syst. 23(2): 197-218 (2005) - [c11]Chunling Hu, Daniel A. Jiménez, Ulrich Kremer:
Toward an Evaluation Infrastructure for Power and Energy Optimizations. IPDPS 2005 - [c10]Daniel A. Jiménez:
Piecewise Linear Branch Prediction. ISCA 2005: 382-393 - [c9]Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero:
Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. ISHPC 2005: 56-67 - [c8]Daniel A. Jiménez:
Code placement for improving dynamic branch prediction accuracy. PLDI 2005: 107-116 - [c7]Miquel Pericàs, Adrián Cristal
Chained In-Order/Out-of-Order DoubleCore Architecture. SBAC-PAD 2005: 209-217 - 2004
- [c6]Ravi V. Batchu, Daniel A. Jiménez:
Exploiting Procedure Level Locality to Reduce Instruction Cache Misses. Interaction between Compilers and Computer Architectures 2004: 75-84 - 2003
- [c5]Daniel A. Jiménez:
Reconsidering Complex Branch Predictors. HPCA 2003: 43-52 - [c4]Daniel A. Jiménez:
Fast Path-Based Neural Branch Prediction. MICRO 2003: 243-252 - 2002
- [j1]Daniel A. Jiménez, Calvin Lin:
Neural methods for dynamic branch prediction. ACM Trans. Comput. Syst. 20(4): 369-397 (2002) - 2001
- [c3]Daniel A. Jiménez, Heather L. Hanson, Calvin Lin:
Boolean Formula-Based Branch Prediction for Future Technologies. IEEE PACT 2001: 97-106 - [c2]Daniel A. Jiménez, Calvin Lin:
Dynamic Branch Prediction with Perceptrons. HPCA 2001: 197-206 - 2000
- [c1]Daniel A. Jiménez, Stephen W. Keckler, Calvin Lin:
The impact of delay on the design of branch predictors. MICRO 2000: 67-76
Coauthor Index
Paul Gratz
aka: Paul V. Gratz
aka: Paul V. Gratz
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