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S. Arash Mirhaj
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2020 – today
- 2022
- [j4]Keertana Settaluri
, Zhaokai Liu
Automated Design of Analog Circuits Using Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 2794-2807 (2022)
2010 – 2019
- 2015
- [c1]Zuow-Zun Chen, Yen-Hsiang Wang, Jaewook Shin, Yan Zhao, Seyed Arash Mirhaj, Yen-Cheng Kuan
14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. ISSCC 2015: 1-3 - 2011
- [j3]Arashk Norouzpour-Shirazi, S. Arash Mirhaj, Shahin Jafarabadi-Ashtiani
Linearity improvement of open-loop NMOS source-follower sample and hold circuits. IET Circuits Devices Syst. 5(1): 1-7 (2011) - [j2]S. Arash Mirhaj, Arashk Norouzpour-Shirazi, Shahin Jafarabadi-Ashtiani
High speed sample and hold design using closed-loop pole-zero cancelation. Microelectron. J. 42(12): 1353-1358 (2011)
2000 – 2009
- 2008
- [j1]Arashk Norouzpour-Shirazi, S. Arash Mirhaj, Shahin Jafarabadi-Ashtiani
A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 971-975 (2008)
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