default search action
Tetsushi Koide
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2022
- [j34]Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Toru Tamaki, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka:
Classification with CNN features and SVM on Embedded DSP Core for Colorectal Magnified NBI Endoscopic Video Image. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(1): 25-34 (2022) - [j33]Masayuki Odagawa, Tetsushi Koide, Toru Tamaki, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka:
Feasibility Study for Computer-Aided Diagnosis System with Navigation Function of Clear Region for Real-Time Endoscopic Video Image on Customizable Embedded DSP Cores. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(1): 58-62 (2022) - 2021
- [j32]Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka, Takayuki Sugawara, Hiroshi Toishi, Masayuki Tsuji, Nobuo Tamba:
A Hardware Implementation on Customizable Embedded DSP Core for Colorectal Tumor Classification with Endoscopic Video toward Real-Time Computer-Aided Diagnosais System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(4): 691-701 (2021) - [c68]Tetsushi Koide, Ryuichi Michida, Seiji Izakura, Yuki Hayashida, Yumi Aoyama:
Sweat Droplets Detection Using Image Segmentation on Skin Surface for Evaluation of Sweating Responses to Thermal Stimulus in Atopic Dermatitis. MWSCAS 2021: 559-562 - [c67]Ryuichi Michida, Seiji Izakura, Tetsushi Koide, Yuki Hayashida, Yumi Aoyama:
An Image Segmentation Method for Automatic Analysis of Skin Surface Structure in Atopic Dermatitis by the Impression Mold Technique. MWSCAS 2021: 563-566 - 2020
- [c66]Kyosuke Kageyama, Kensuke Watanabe, Akimitsu Hamai, Takeshi Kumaki, Tetsushi Koide:
Acceleration of arithmetic processing with CAM-based massive-parallel SIMD matrix core. MWSCAS 2020: 486-489 - [c65]Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Toru Tamaki
, Bisser Raytchev, Kazufumi Kaneda, Shinji Tanaka:
Classification Method with CNN features and SVM for Computer-Aided Diagnosis System in Colorectal Magnified NBI Endoscopy. TENCON 2020: 1095-1100
2010 – 2019
- 2019
- [c64]Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Toru Tamaki
A Hardware Implementation of Colorectal Tumor Classification for Endoscopic Video on Customizable DSP Toward Real-Time Computer-Aided Diagnosis System. ISCAS 2019: 1-5 - [c63]Kazunari Inoue, Nozomi Kobori, Atsushi Hirota, Tetsushi Koide, Takumi Okamoto:
An IoT-gateway with the information-centric communication. ISDCS 2019: 1-3 - [c62]Kyosuke Kageyama, Takeshi Kumaki, Tetsushi Koide:
Structuring Element-counting Approach for Morphological Pattern Spectrum-based Image Manipulation Detection. ISDCS 2019: 1-4 - [c61]Toshihiro Kasama, Tetsushi Koide, Wojciech P. Bula, Yukio Yaji, Yoshishige Endo, Ryo Miyake:
Low Cost and Robust Field-Deployable Environmental Sensor for Smart Agriculture. ISDCS 2019: 1-4 - [c60]Hideki Murakami, Yoshiki Tanaka, Jun-ichi Yamashita, Rikako Takeshita, Yasunori Sakane, Takumi Okamoto, Tetsushi Koide:
Development of In-situ Monitoring System for Crop Growth Observation. ISDCS 2019: 1-4 - [c59]Takumi Okamoto, Masayuki Odagawa, Tetsushi Koide, Shinji Tanaka, Toru Tamaki
Feature Extraction of Colorectal Endoscopic Images for Computer-Aided Diagnosis with CNN. ISDCS 2019: 1-4 - 2018
- [c58]Takumi Okamoto, Yasunori Sakane, Tetsushi Koide, Atsushi Ogawa, Masashi Komine, Chiharu Sone, Yoshihiro Kaneta, Yukio Yaji, Kyoko Toyofuku, Takahiro Kamata, Ken Kimura, Yoko Ishikawa, Toshihiro Kasama, Wojciech-Piptr Bula, Yoshishige Endo, Ryo Miyake:
An Image Analysis Method for Lettuce Leaf and Root Growth Analysis in Hydroponic Culture. TENCON 2018: 467-470 - [c57]Takumi Okamoto, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Hiroshi Toishi, Takayuki Sugawara, Masayuki Tsuji, Masayuki Odagawa, Nobuo Tamba, Toru Tamaki
Implementation of Computer-Aided Diagnosis System on Customizable DSP Core for Colorectal Endoscopic Images with CNN Features and SVM. TENCON 2018: 1663-1666 - 2016
- [j31]Tsubasa Hirakawa, Toru Tamaki
Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition. Artif. Intell. Medicine 68: 1-16 (2016) - [j30]Tsubasa Hirakawa, Toru Tamaki
Corrigendum to "Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition" [Artif. Intell. Med. 68 (March 2016) 1-16]. Artif. Intell. Medicine 72: 83 (2016) - [c56]Tsubasa Hirakawa, Toru Tamaki
Discriminative Subtree Selection for NBI Endoscopic Image Labeling. ACCV Workshops (2) 2016: 610-624 - [i4]Toru Tamaki, Shoji Sonoyama, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka:
Computer-Aided Colorectal Tumor Classification in NBI Endoscopy Using CNN Features. CoRR abs/1608.06709 (2016) - [i3]Shoji Sonoyama, Toru Tamaki, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka:
Transfer Learning for Endoscopic Image Classification. CoRR abs/1608.06713 (2016) - [i2]Toru Tamaki, Shoji Sonoyama, Takio Kurita, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka, Kazuaki Chayama:
Domain Adaptation with L2 constraints for classifying images from different endoscope systems. CoRR abs/1611.02443 (2016) - [i1]Tsubasa Hirakawa, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka:
Development of a Real-time Colorectal Tumor Classification System for Narrow-band Imaging zoom-videoendoscopy. CoRR abs/1612.05000 (2016) - 2015
- [c55]Shoji Sonoyama, Tsubasa Hirakawa, Toru Tamaki
Transfer learning for Bag-of-Visual words approach to NBI endoscopic image classification. EMBC 2015: 785-788 - [c54]Takumi Okamoto, Tetsushi Koide, Koki Sugi, Tatsuya Shimizu, Anh-Tuan Hoang, Toru Tamaki
Image segmentation of pyramid style identifier based on Support Vector Machine for colorectal endoscopic images. EMBC 2015: 2997-3000 - [c53]Shoji Sonoyama, Toru Tamaki
Trade-off between speed and performance for colorectal endoscopic NBI image classification. Image Processing 2015: 94132D - 2014
- [c52]Takeshi Kumaki, Takeshi Fujino, Tetsushi Koide:
Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor. APCCAS 2014: 359-362 - [c51]Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto:
Low cost hardware implementation for traffic sign detection system. APCCAS 2014: 363-366 - [c50]Tetsushi Koide, Anh-Tuan Hoang, Takumi Okamoto, Satoshi Shigemi, Tsubasa Mishima, Toru Tamaki
FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification. APCCAS 2014: 651-654 - [c49]Tsubasa Hirakawa, Tom Tamaki, Bisser Raytchev
SVM-MRF segmentation of colorectal NBI endoscopic images. EMBC 2014: 4739-4742 - [c48]Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto, Mutsumi Omori:
Pipeline scanning architecture with computation reduction for rectangle pattern matching in real-time traffic sign detection. ISCAS 2014: 1532-1535 - [c47]Tsubasa Mishima, Satoshi Shigemi, Anh-Tuan Hoang, Tetsushi Koide, Toru Tamaki
FPGA implementation of feature extraction for colorectal endoscopic images with NBI magnification. ISCAS 2014: 2515-2518 - [c46]Masaharu Yamamoto, Anh-Tuan Hoang, Mutsumi Omori, Tetsushi Koide:
Compact hardware oriented number recognition algorithm for real-time speed traffic-sign recognition. ISCAS 2014: 2535-2538 - 2013
- [c45]Tsubasa Hirakawa, Toru Tamaki
Labeling colorectal NBI zoom-videoendoscope image sequences with MRF and SVM. EMBC 2013: 4831-4834 - [c44]Keisuke Konishi, Takeshi Tanaka, Tetsushi Koide:
Power electronics education using the integrated circuit consistent education system and TCAD. FIE 2013: 1456-1458 - [c43]Tsubasa Hirakawa, Toru Tamaki
Smoothing posterior probabilities with a particle filter of dirichlet distribution for stabilizing colorectal NBI endoscopy recognition. ICIP 2013: 621-625 - 2012
- [j29]Fengwei An
A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching. IEICE Trans. Inf. Syst. 95-D(9): 2327-2338 (2012) - [j28]Hans Jürgen Mattausch, Wataru Imafuku, Akio Kawabata, Tania Ansari, Masahiro Yasuda, Tetsushi Koide:
Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping. IEEE J. Solid State Circuits 47(6): 1448-1459 (2012) - 2011
- [j27]Ali Ahmadi
An associative memory-based learning model with an efficient hardware implementation in FPGA. Expert Syst. Appl. 38(4): 3499-3513 (2011) - [j26]Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Masaharu Tagami, Masakatsu Ishizaki:
Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems. IEICE Trans. Inf. Syst. 94-D(9): 1742-1754 (2011) - [j25]Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto:
A Scalable Massively Parallel Processor for Real-Time Image Processing. IEEE J. Solid State Circuits 46(10): 2363-2373 (2011) - [c42]Fengwei An
Real-time hybrid learning and recognition system with software-hardware cooperation. ROBIO 2011: 2505-2510 - 2010
- [j24]Koh Johguchi, Akihiro Kaya, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide, Norio Sadachika:
Measurement-Based Ring Oscillator Variation Analysis. IEEE Des. Test Comput. 27(5): 6-13 (2010) - [c41]Hans Jürgen Mattausch, Wataru Imafuku, Tania Ansari, Akio Kawabata, Tetsushi Koide:
Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping. ESSCIRC 2010: 538-541 - [c40]Akio Kawabata, Tetsushi Koide, Hans Jürgen Mattausch:
Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding. ICNC 2010: 15-19 - [c39]Tetsushi Koide, R. Kimura, T. Sugahara, K. Okazaki, Hans Jürgen Mattausch:
Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size. ICNC 2010: 128-132 - [c38]Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto:
A scalable massively parallel processor for real-time image processing. ISSCC 2010: 334-335
2000 – 2009
- 2008
- [j23]Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Trans. Electron. 91-C(9): 1409-1418 (2008) - 2007
- [j22]Koh Johguchi, Yuya Mukuda, Ken-ichi Aoyama, Hans Jürgen Mattausch, Tetsushi Koide:
A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin. IEICE Electron. Express 4(2): 21-25 (2007) - [j21]Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Trans. Inf. Syst. 90-D(1): 334-345 (2007) - [j20]Takeshi Kumaki, Yutaka Kono, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch:
Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory. IEICE Trans. Inf. Syst. 90-D(1): 346-354 (2007) - [j19]Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi
Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(6): 1240-1243 (2007) - [j18]Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Trans. Inf. Syst. 90-D(8): 1312-1315 (2007) - [j17]Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka:
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Trans. Electron. 90-C(11): 2157-2160 (2007) - [c37]Koh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide:
A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. ESSCIRC 2007: 320-323 - [c36]Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS 2007: 525-528 - 2006
- [j16]Takashi Morimoto, Hidekazu Adachi, Osamu Kiriyama, Tetsushi Koide, Hans Jürgen Mattausch:
Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation. IEICE Trans. Inf. Syst. 89-D(3): 1299-1302 (2006) - [j15]Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Trans. Electron. 89-C(11): 1612-1619 (2006) - [c35]Takashi Morimoto, Hidekazu Adachi, Kousuke Yamaoka, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch:
An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. APCCAS 2006: 944-947 - [c34]Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa:
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS 2006: 1297-1300 - [c33]Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi
Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. APCCAS 2006: 1309-1312 - [c32]Takeshi Kumaki, Y. Kouno, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch:
Application of Multi-ported CAM for Parallel Coding. APCCAS 2006: 1859-1862 - [c31]Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch:
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. ASP-DAC 2006: 176-181 - [c30]Ali Ahmadi, M. Arifin Ritonga, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide:
A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA. IEEE Congress on Evolutionary Computation 2006: 687-693 - [c29]Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch:
Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. ISCAS 2006 - 2005
- [j14]Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. 88-C(4): 622-629 (2005) - [j13]Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide:
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Trans. Electron. 88-C(6): 1332-1342 (2005) - [j12]Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits 40(1): 245-253 (2005) - [j11]Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide:
Chip size and performance evaluations of shared cache for on-chip multiprocessor. Syst. Comput. Jpn. 36(9): 1-13 (2005) - [c28]Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch:
A low-power video segmentation LSI with boundary-active-only architecture. ASP-DAC 2005: 13-14 - [c27]Ali Ahmadi
A parallel hardware design for parametric active contour models. AVSS 2005: 609-613 - [c26]Takashi Morimoto, Osamu Kiriyama, Yohmei Harada, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch:
Object tracking in video pictures based on image segmentation and pattern matching. ISCAS (4) 2005: 3215-3218 - [c25]Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch:
Design of superscalar processor with multi-bank register file. ISCAS (4) 2005: 3507-3510 - [c24]Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) 2005: 5202-5205 - 2004
- [j10]Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch:
Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation. IEICE Trans. Inf. Syst. 87-D(2): 500-503 (2004) - [c23]Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch:
350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. ASP-DAC 2004: 531-532 - [c22]Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch:
Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. ASP-DAC 2004: 543-544 - [c21]Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka:
Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. ASP-DAC 2004: 551-552 - 2003
- [c20]Tetsushi Koide, Hans Jürgen Mattausch, Yuji Yano, Takayuki Gyohten, Yoshihiro Soda:
A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. ASP-DAC 2003: 591-592 - [c19]Zhaomin Zhu, Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Tetsuo Hironaka:
A novel hierarchical multi-port cache. ESSCIRC 2003: 405-408 - 2002
- [j9]Shinya Yamasaki, Shingo Nakaya, Shin'ichi Wakabayashi, Tetsushi Koide:
A Performance-Driven Floorplanning Method with Interconnect Performance Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2775-2784 (2002) - [j8]Hans Jürgen Mattausch, Takayuki Gyohten, Yoshihiro Soda, Tetsushi Koide:
Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance. IEEE J. Solid State Circuits 37(2): 218-227 (2002) - [j7]Shigeki Takekawa, Shin'ichi Wakabayashi, Tetsushi Koide:
A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. Syst. Comput. Jpn. 33(12): 87-96 (2002) - 2001
- [j6]Tetsushi Koide, S. Shinmori, H. Ishii:
Topological optimization with a network reliability constraint. Discret. Appl. Math. 115(1-3): 135-149 (2001) - [j5]Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide:
Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. Syst. Comput. Jpn. 32(1): 29-37 (2001) - 2000
- [c18]Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Masataka Yamane, Hajime Ueno:
Genetic algorithm accelerator GAA-II. ASP-DAC 2000: 9-10 - [c17]Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi:
Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. ASP-DAC 2000: 99-104 - [c16]Shingo Nakaya, Tetsushi Koide, Shin'ichi Wakabayashi:
An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair. ISCAS 2000: 65-68
1990 – 1999
- 1999
- [j4]Tetsushi Koide, Shin'ichi Wakabayashi:
A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. Integr. 27(1): 57-76 (1999) - [c15]Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta:
An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. ASP-DAC 1999: 37-40 - [c14]Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide:
Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. ASP-DAC 1999: 181-184 - 1998
- [c13]Tetsushi Koide, Shin'ichi Wakabayashi:
A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. ASP-DAC 1998: 577-583 - [c12]Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide:
Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. PPSN 1998: 1028-1037 - 1997
- [j3]Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida:
A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. Integr. 24(1): 53-77 (1997) - [c11]Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru:
Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. ASP-DAC 1997: 133-140 - 1996
- [j2]Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A three-layer over-the-cell multi-channel router for a new cell model. Integr. 21(3): 171-189 (1996) - [j1]Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
Pin assignment with global routing for VLSI building block layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1575-1583 (1996) - 1995
- [c10]Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A new system partitioning method under performance and physical constraints for multi-chip modules. ASP-DAC 1995 - [c9]Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru:
A new performance driven placement method with the Elmore delay model for row based VLSIs. ASP-DAC 1995 - [c8]Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A three-layer over-cell multi-channel routing method for a new cell model. ASP-DAC 1995 - [c7]Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida:
An MCM Routing Algorithm Considering Crosstalk. ISCAS 1995: 211-214 - [c6]Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida:
A Verification Algorithm for Logic Circuits with Internal Variables. ISCAS 1995: 1920-1923 - 1994
- [c5]Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A Floorplanning Method with Topological Constraint Manipulation. ISCAS 1994: 165-168 - [c4]Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida:
A Systolic Graph Partitioning Algorithm for VLSI Design. ISCAS 1994: 225-228 - 1993
- [c3]Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A new global routing algorithm for over-the-cell routing in standard cell layouts. EURO-DAC 1993: 116-121 - [c2]Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida:
Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. ISCAS 1993: 2059-2062 - 1992
- [c1]Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
An optimal channel pin assignment with multiple intervals for building block layout. EURO-DAC 1992: 348-353
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-28 20:33 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: