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Farhad Mehdipour
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2020 – today
- 2024
- [c46]Farhad Mehdipour, Ari Aharari:
Enhancing COVID-19 Data Analysis through HCI-Driven AI and IoT Integration. GCCE 2024: 840-843 - [c45]Ari Aharari, Farhad Mehdipour:
Inventory Control in Food Industry Using an AI-Driven Precision Counting. GCCE 2024: 844-847 - [c44]Marziyeh Bahrami
, Abolfazl Toroghi Haghighat
Empowering Medical Staff: IoT-Based Smart Shield for Early Detection of Acute Respiratory Diseases. ICMIP 2024: 72-77 - 2020
- [c43]Firas Al-Ali, Thilina Doremure Gamage, Hewa W. T. S. Nanayakkara, Farhad Mehdipour, Sayan Kumar Ray:
Novel Casestudy and Benchmarking of AlexNet for Edge AI: From CPU and GPU to FPGA. CCECE 2020: 1-4
2010 – 2019
- 2019
- [j17]Kalpana Nand, Nilufar Baghaei
Engaging children with educational content via Gamification. Smart Learn. Environ. 6(1): 6 (2019) - [c42]Bahman A. Sassani Sarrafpour, Andrew David, Xiaosong Li, Farhad Mehdipour:
AgentPi: An IoT Enabled Motion CCTV Surveillance System. DASC/PiCom/DataCom/CyberSciTech 2019: 454-458 - [c41]Bahman A. Sassani Sarrafpour, Rosario Del Pilar Soria Choque, Blake Mitchell Paul, Farhad Mehdipour:
Commercial Security Scanning: Point-on-Sale (POS) Vulnerability and Mitigation Techniques. DASC/PiCom/DataCom/CyberSciTech 2019: 493-498 - [c40]Firas Al-Ali, Thilina Doremure Gamage, Hewa W. T. S. Nanayakkara, Farhad Mehdipour, Sayan Kumar Ray:
Supercomputer Networks in the Datacenter: Benchmarking the Evolution of Communication Granularity from Macroscale down to Nanoscale. ITNAC 2019: 1-6 - [c39]Solmaz Rastegar, Hamid Gholamhosseini
Estimating Systolic Blood Pressure Using Convolutional Neural Networks. pHealth 2019: 143-149 - [p1]Farhad Mehdipour, Bahman Javadi, Aniket Mahanti
Fog Computing Realization for Big Data Analytics. Fog and Edge Computing 2019: 259-290 - 2018
- [c38]Farhad Mehdipour, Mohsen Pashna, Aniket Mahanti
A 3-Tier Solution for Facilitating STEM Education in Primary Schools. LaTiCE 2018: 1-5 - 2017
- [j16]Navid Rahmanikia
Performance evaluation metrics for ring-oscillator-based temperature sensors on FPGAs: A quality factor. Integr. 57: 81-100 (2017) - 2016
- [j15]Farhad Mehdipour, Hamid Noori, Bahman Javadi:
Energy-Efficient Big Data Analytics in Datacenters. Adv. Comput. 100: 59-101 (2016) - [j14]Ahmed Medhat, Ahmed Shalaby
Adaptive low-complexity motion estimation algorithm for high efficiency video coding encoder. IET Image Process. 10(6): 438-447 (2016) - [j13]Bagher Salami, Hamid Noori, Farhad Mehdipour, Mohammadreza Baharani
Physical-aware predictive dynamic thermal management of multi-core processors. J. Parallel Distributed Comput. 95: 42-56 (2016) - [j12]Mostafa Said
A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias. Microprocess. Microsystems 43: 26-46 (2016) - [c37]Farhad Mehdipour, Bahman Javadi, Aniket Mahanti
FOG-Engine: Towards Big Data Analytics in the Fog. DASC/PiCom/DataCom/CyberSciTech 2016: 640-646 - [c36]Mirza Ferdous Rahman, Farhad Mehdipour, Hiroshi Furukawa:
Modeling the Impact of Clustering with Random Event Arrival on the Lifetime of WSN. ICNCC 2016: 292-296 - [c35]Bahman A. Sassani, Charly Abarro, Ivan Pitton, Craig Young, Farhad Mehdipour:
Analysis of NTP DRDoS attacks' performance effects and mitigation techniques. PST 2016: 421-427 - 2015
- [j11]Krishna Chaitanya Nunna, Farhad Mehdipour, Antoine Trouvé, Kazuaki J. Murakami:
A survey on big data processing infrastructure: evolving role of FPGA. Int. J. Big Data Intell. 2(3): 145-156 (2015) - [j10]Masoud Daneshtalab
Special Issue on Emerging Many-Core Systems for Exascale Computing. ACM J. Emerg. Technol. Comput. Syst. 11(4): 39:1-39:2 (2015) - [c34]Navid Rahmanikia
Exploring Efficiency of Ring Oscillator-Based Temperature Sensor Networks on FPGAs (Abstract Only). FPGA 2015: 264 - [c33]Ali Akbari, Saadat Pour-Mozafari, Hamid Noori, Farhad Mehdipour:
Dynamic Task Priority Scaling for Thermal Management of Multi-core Processors with Heavy Workload. ACM Great Lakes Symposium on VLSI 2015: 373-378 - 2014
- [j9]Hiroshi Kataoka, Hiroaki Honda, Farhad Mehdipour, Nobuyuki Yoshikawa
A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits. IEICE Trans. Electron. 97-C(3): 141-148 (2014) - [c32]Ahmed Medhat, Ahmed Shalaby
A highly parallel SAD architecture for motion estimation in HEVC encoder. APCCAS 2014: 280-283 - [c31]Bagher Salami, Mohammadreza Baharani
Physical-aware task migration algorithm for dynamic thermal management of SMT multi-core processors. ASP-DAC 2014: 292-297 - [c30]Javad Mohebbi Najm Abad
A neuro-fuzzy fan speed controller for dynamic thermal management of multi-core processors. Conf. Computing Frontiers 2014: 29:1-29:2 - [c29]Ahmed Medhat, Ahmed Shalaby
Fast center search algorithm with hardware implementation for motion estimation in HEVC encoder. ICECS 2014: 155-158 - [c28]Farhad Mehdipour:
Smart Field Monitoring: An Application of Cyber-Physical Systems in Agriculture (Work in Progress). IIAI-AAI 2014: 181-184 - [c27]Mostafa Said, Farhad Mehdipour, Kazuaki J. Murakami, Mohamed El-Sayed:
A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias. MES@ISCA 2014: 9-16 - [c26]Mostafa Said, Mohamed El-Sayed, Farhad Mehdipour, Nobuaki Miyakawa:
Keep-Out-Zone analysis for three-dimensional ICs. VLSI-DAT 2014: 1-4 - [e1]Farhad Mehdipour, Giorgos Dimitrakopoulos:
Proceedings of the 2014 International Workshop on Network on Chip Architectures, NoCArc '14, Cambridge, United Kingdom, December 13-14, 2014. ACM 2014, ISBN 978-1-4503-3064-0 [contents] - 2013
- [c25]Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila
MD: Minimal path-based fault-tolerant routing in on-Chip Networks. ASP-DAC 2013: 35-40 - [c24]Hany S. Hussein
Low complexity independent multi-view video coding. CCNC 2013: 37-42 - [c23]Mostafa Said, Farhad Mehdipour, Mohamed El-Sayed:
Improving Performance and Fabrication Metrics of Three-Dimensional ICs by Multiplexing Through-Silicon Vias. DSD 2013: 925-932 - [c22]Krishna Chaitanya Nunna, Farhad Mehdipour, Kazuaki J. Murakami:
Early stage power management for 3D FPGAs considering hierarchical routing resources. ACM Great Lakes Symposium on VLSI 2013: 31-36 - [c21]Farhad Mehdipour, Krishna Chaitanya Nunna, Kazuaki J. Murakami:
A Smart Cyber-physical Systems-Based Solution for Pest Control (Work in Progress). GreenCom/iThings/CPScom 2013: 1248-1253 - 2012
- [j8]Hamid Noori
Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization. J. Supercomput. 60(2): 196-222 (2012) - [c20]Farhad Mehdipour, Krishna Chaitanya Nunna, Koji Inoue, Kazuaki J. Murakami:
A Three-Dimensional Integrated Accelerator. DSD 2012: 148-151 - [c19]Krishna Chaitanya Nunna, Farhad Mehdipour, Kazuaki J. Murakami:
Thermal-aware partitioning for 3D FPGAs. FPL 2012: 475-476 - [c18]Krishna Chaitanya Nunna, Farhad Mehdipour, Masayoshi Yoshimura, Kazuaki J. Murakami:
Methodology for early estimation of hierarchical routing resources in 3D FPGAs. VLSI-SoC 2012: 213-218 - 2011
- [j7]Farhad Mehdipour, Hiroaki Honda, Koji Inoue, Hiroshi Kataoka, Kazuaki J. Murakami:
A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuits. J. Syst. Archit. 57(1): 169-179 (2011) - [c17]Farhad Mehdipour, Krishna Chaitanya Nunna, Lovic Gauthier, Koji Inoue, Kazuaki J. Murakami:
A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack. 3DIC 2011: 1-4 - [c16]Farhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, Koji Inoue, Kazuaki J. Murakami:
Routing architecture and algorithms for a superconductivity circuits-based computing hardware. CCECE 2011: 977-980 - 2010
- [c15]Farhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, Koji Inoue, Irina Kataeva, Kazuaki J. Murakami, Hiroyuki Akaike, Akira Fujimaki:
Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits. DATE 2010: 993-996
2000 – 2009
- 2009
- [j6]Farhad Mehdipour, Hamid Noori
Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3182-3192 (2009) - [c14]Farhad Mehdipour, Hamid Noori
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. ASP-DAC 2009: 564-569 - 2008
- [j5]Farhad Mehdipour, Hamid Noori
A gravity-directed temporal partitioning approach. IEICE Electron. Express 5(10): 366-373 (2008) - [j4]Hamid Noori
A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions. IEICE Trans. Electron. 91-C(4): 497-508 (2008) - [j3]Hamid Noori
An architecture framework for an adaptive extensible processor. J. Supercomput. 45(3): 313-340 (2008) - [c13]Farhad Mehdipour, Hamid Noori
Design space exploration for a coarse grain accelerator. ASP-DAC 2008: 685-690 - [c12]Hamid Noori
Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension. ISLPED 2008: 241-246 - 2007
- [j2]Farhad Mehdipour, Hamid Noori
Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. IEICE Trans. Inf. Syst. 90-D(12): 1956-1966 (2007) - [c11]Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Maziar Goudarzi
Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. DATE 2007: 325-330 - [c10]Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami:
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. ICESS 2007: 249-260 - [c9]Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Zamani
An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. VLSI-SoC 2007: 151-156 - 2006
- [j1]Farhad Mehdipour, Morteza Saheb Zamani
An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. Microprocess. Microsystems 30(1): 52-62 (2006) - [c8]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Mehdi Sedighi, Koji Inoue:
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. Asia-Pacific Computer Systems Architecture Conference 2006: 219-230 - [c7]Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki J. Murakami, Hamid Noori:
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. ERSA 2006: 227-230 - [c6]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Koji Inoue, Mehdi Sedighi:
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. EUC 2006: 722-731 - [c5]Hamid Noori
A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. FPL 2006: 1-4 - [c4]Farhad Mehdipour, Morteza Saheb Zamani
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. IPDPS 2006 - 2005
- [c3]Farhad Mehdipour, Morteza Saheb Zamani
Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. DSD 2005: 372-378 - [c2]Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghian, Farhad Mehdipour:
A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms. FPT 2005: 307-308
1990 – 1999
- 1999
- [c1]Morteza Saheb Zamani, Farhad Mehdipour:
An efficient method for placement of VLSI designs with Kohonen map. IJCNN 1999: 3328-3331
Coauthor Index
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