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Jason Howard
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2020 – today
- 2024
- [j9]Vignesh Sundaravarathan, Husain Alqalaf, Asif Siddiqui, Kiju Kim, Sanghee Lee, Martin Reisslein
, Akhilesh S. Thyagaturu, Nick Ross
Cross-Domain Solutions (CDS): A Comprehensive Survey. IEEE Access 12: 163551-163620 (2024) - [j8]Jason Howard
The First Direct Mesh-to-Mesh Photonic Fabric. IEEE Micro 44(3): 25-32 (2024) - 2023
- [j7]Sriram Aananthakrishnan
The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor. IEEE Micro 43(5): 78-87 (2023) - [c12]Jason Howard:
The First Direct Mesh-to-Mesh Photonic Fabric. HCS 2023: 1-17 - 2020
- [i1]Sriram Aananthakrishnan, Nesreen K. Ahmed, Vincent Cavé, Marcelo Cintra, Yigit Demir, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Ivan Ganev, Wim Heirman, Hans-Christian Hoppe, Jason Howard, Ibrahim Hur, Midhunchandra Kodiyath, Samkit Jain, Daniel S. Klowden, Marek M. Landowski, Laurent Montigny, Ankit More, Przemyslaw Ossowski, Robert Pawlowski, Nick Pepperling, Fabrizio Petrini, Mariusz Sikora, Balasubramanian Seshasayee, Shaden Smith, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche, Izajasz P. Wrosz
PIUMA: Programmable Integrated Unified Memory Architecture. CoRR abs/2010.06277 (2020)
2010 – 2019
- 2014
- [c11]Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar:
Resiliency for many-core system on a chip. ASP-DAC 2014: 388-389 - 2012
- [c10]Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar
An IA-32 processor with a wide voltage operating range in 32nm CMOS. Hot Chips Symposium 2012: 1-37 - [c9]Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. ISSCC 2012: 66-68 - 2011
- [j6]Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. IEEE J. Solid State Circuits 46(1): 173-183 (2011) - [j5]Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE J. Solid State Circuits 46(1): 184-193 (2011) - 2010
- [c8]Jason Howard, Saurabh Dighe, Yatin Vasant Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. ISSCC 2010: 108-109 - [c7]Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. ISSCC 2010: 174-175 - [c6]Timothy G. Mattson, Michael Riepen, Thomas Lehnig, Paul Brett, Werner Haas, Patrick Kennedy, Jason Howard, Sriram R. Vangal, Nitin Borkar, Gregory Ruhl, Saurabh Dighe:
The 48-core SCC Processor: the Programmer's View. SC 2010: 1-11
2000 – 2009
- 2009
- [j4]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits 44(1): 174-185 (2009) - 2008
- [j3]Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Vasant Hoskote, Nitin Borkar, Shekhar Borkar:
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. IEEE J. Solid State Circuits 43(1): 29-41 (2008) - [c5]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC 2008: 274-275 - 2007
- [j2]Muhammad M. Khellah
A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. IEEE J. Solid State Circuits 42(1): 233-242 (2007) - [c4]Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Priya Iyer, Arvind P. Singh
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. ISSCC 2007: 98-589 - [c3]James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. ISSCC 2007: 292-604 - 2006
- [c2]Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. ISSCC 2006: 2572-2581 - [c1]Priya Iyer, Shailendra Jain, Bryan Casper, Jason Howard:
Testing High-Speed IO Links Using On-Die Circuitry. VLSI Design 2006: 807-810 - 2003
- [j1]Yatin Vasant Hoskote, Bradley A. Bloechel, Gregory E. Dermer, Vasantha Erraguntla, David Finan, Jason Howard, Dan Klowden, Siva G. Narendra, Greg Ruhl, James W. Tschanz, Sriram R. Vangal, Venkat Veeramachaneni, Howard Wilson, Jianping Xu, Nitin Borkar:
A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. IEEE J. Solid State Circuits 38(11): 1866-1875 (2003)
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