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Geun Rae Cho
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2010 – 2019
- 2014
- [c7]Moon Gi Seok, Daejin Park, Geun Rae Cho, Tag Gon Kim:
Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability. VLSI-SoC 2014: 1-6 - 2013
- [j3]Geun Rae Cho, Kyung Woon Hwang, Tag Gon Kim:
A high supply voltage bandgap reference circuit using drain-extended MOS devices. IEICE Electron. Express 10(8): 20130142 (2013)
2000 – 2009
- 2004
- [j2]Geun Rae Cho, Tom Chen:
Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2): 229-242 (2004) - 2003
- [c6]Geun Rae Cho, Tom Chen:
Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. ISQED 2003: 55-60 - [c5]Geun Rae Cho, Tom Chen:
On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. VLSI Design 2003: 513- - 2002
- [c4]Geun Rae Cho, Tom Chen:
On The Impact of Technology Scaling On Mixed PTL/Static Circuits. ICCD 2002: 322-326 - [c3]Geun Rae Cho, Tom Chen:
Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. ISQED 2002: 458-463 - [c2]Geun Rae Cho, Tom Chen:
On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. IWLS 2002: 289-294 - [c1]Geun Rae Cho, Tom Chen:
Applications of Evolution Algorithms to the synthesis of single/Dual-rail mixed PTL/Static Logic for low-Power Applications. SEAL 2002: 446-465 - 2001
- [j1]Geun Rae Cho, Tom Chen:
On Mixed PTL/Static Logic for Low-power and High-speed Circuits. VLSI Design 12(3): 399-406 (2001)
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