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Tzung-Je Lee
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2020 – today
- 2024
- [j26]Tzung-Je Lee
, Yu-Wei Liu:
High efficiency active rectifier with low-power self-biased comparator for low-frequency piezoelectric vibration energy harvesting of AUV. Microelectron. J. 146: 106137 (2024) - [j25]Chua-Chin Wang
A 1-6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD. Microelectron. J. 151: 106355 (2024) - [j24]Chua-Chin Wang
A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 4961-4972 (2024) - [c29]Jhih-Ying Ke, Lean Karlo Santos Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang:
GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process. AICAS 2024: 95-99 - [c28]Tzung-Je Lee, Ji-Hau Chiou:
A 3.2-GHz 0.3/0.5 V 16-nm FinFET I/O Buffer With Low-Power PVT Compensation Circuit. ISCAS 2024: 1-5 - 2023
- [j23]Chua-Chin Wang
A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. Circuits Syst. Signal Process. 42(4): 2283-2304 (2023) - [j22]Chua-Chin Wang
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process. Integr. 90: 245-260 (2023) - [j21]Tzung-Je Lee
High-Sensitivity PTAT Current Generator Using PTAT and CTAT Current Subtraction Method for Temperature Sensor With Frequency Output. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3922-3926 (2023) - [c27]Jhih-Ying Ke, Lean Karlo S. Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang:
A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process. APCCAS 2023: 271-275 - [c26]Tzung-Je Lee, Hsieng-Han Chen:
±3 A Bidirectional Current Sensor for 57.6 V Li-ion Battery Management System of AUV. ICCE-Taiwan 2023: 277-278 - [c25]Tzung-Je Lee, Yu-Wei Liu, Yu-Cheng Lin:
Real-time IR Image Processing Interface on FPGA with Histogram Equalization and Non-Uniform Correction. ICCE-Taiwan 2023: 709-710 - [c24]Tzung-Je Lee, Ding-Ze Chang:
91.282% Efficiency SIDO Buck-Buck Converter with Separate Positive and Negative Output Voltage in 40 nm CMOS Process. ISCAS 2023: 1-4 - [c23]Tzung-Je Lee, Shih-Hsien Kuo:
3.2 Gbps Output Driver With Dual Low Voltage Modes and Low Power PVT Compensation Circuit. ISCAS 2023: 1-4 - [c22]Tzung-Je Lee, Hung-Hsiang Chang, Chien-Hsiang Chao:
High Bandwidth Efficiency FPGA-based Underwater Acoustic Transceiver with Adaptive-SFDR DDFS. ISOCC 2023: 39-40 - [c21]Tzung-Je Lee, Yin-Wen Lo:
Temperature Sensor with 292.3 nA/°C Sensitivity Using Double Current Subtraction. ISOCC 2023: 49-50 - [c20]Tzung-Je Lee, Kuo-Hsun Tu:
10-bit 250-KS/s M-2M Digital-to-Analog Converter with 4-4-2 Segmentation for Sonar System. ISOCC 2023: 95-96 - [c19]Tzung-Je Lee, Meng-Lin Tsai:
A High Dynamic-Range Readout Circuit with Differential Resistance-to-Time Conversion for Gas Sensor. NEWCAS 2023: 1-4 - 2022
- [c18]Tzung-Je Lee, Bo-Hao Liao, Chua-Chin Wang:
Wide Lock-in Range CDR with Modified DQFD and Coarse-fine Tuning Technique. ICICDT 2022: 61-64 - [c17]Tzung-Je Lee, Hung-Hsiang Chang:
Fast-Transient LDO Regulator with RC-less Low-Impedance Buffer and PVT Compensation. ISOCC 2022: 11-12 - [c16]Tzung-Je Lee, Kuo-Hsun Tu:
Wide Dynamic Range Temperature Sensor Using High Sensitivity PTAT Current Generator. ISOCC 2022: 17-18 - 2021
- [j20]Chua-Chin Wang
2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process. Circuits Syst. Signal Process. 40(6): 2824-2840 (2021) - [j19]Chua-Chin Wang
High-Accuracy Impedance Read-out Circuit for BIA-type Biomedical Sensors. Circuits Syst. Signal Process. 40(9): 4187-4195 (2021) - [j18]Chua-Chin Wang
An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS. Microelectron. J. 118: 105295 (2021) - [c15]Tzung-Je Lee, Wen-Shou Yang, Chua-Chin Wang:
A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology. APCCAS 2021: 33-36 - [c14]Tzung-Je Lee, Wen-Jian Su, Lean Karlo S. Tolentino
A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment. APCCAS 2021: 153-156 - [c13]Tzung-Je Lee, Yu-Wei Liu:
12 V PZE Harvesting Circuit For AUV Using Boost Converter with Resistor Matching Controller. ISOCC 2021: 133-134 - 2020
- [j17]Tzung-Je Lee
A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique. IEEE Trans. Circuits Syst. 67-II(11): 2707-2711 (2020)
2010 – 2019
- 2019
- [j16]Chua-Chin Wang
500 MHz 90 nm CMOS 2 \(\times \) VDD Digital Output Buffer Immunity to Process and Voltage Variations. Circuits Syst. Signal Process. 38(2): 556-568 (2019) - [j15]Tzung-Je Lee
A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 116-120 (2019) - [c12]Tzung-Je Lee, Chia-Hsin Hsu, Chua-Chin Wang:
High Efficiency Buck Converter with Wide Load Current Range using Dual-Mode of PWM and PSM. ISCAS 2019: 1-4 - 2018
- [j14]Tzung-Je Lee, Wei-Chih Hsiao:
Delay-Time-Compensated Peak Detector for Medium-Frequency Band. Circuits Syst. Signal Process. 37(1): 2-18 (2018) - 2017
- [j13]Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U-Fat Chio, Chua-Chin Wang
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3166-3174 (2017) - [c11]Tzung-Je Lee, Guan-Jhang Li:
HV voltage sensor for 16 series li-ion battery cells using chopper stabilized amplifier. ISOCC 2017: 196-197 - 2016
- [j12]Tzung-Je Lee, Wei-Chih Hsiao:
PVT-independent dB-linear reconfigured local-feedback digital variable gain amplifier. Microelectron. J. 50: 20-28 (2016) - [c10]Tzung-Je Lee, Wun-Cing Yu, You-Ting Liu:
16 Series Li-ion battery cells current sensor. ICCE-TW 2016: 1-2 - [c9]Tzung-Je Lee:
HV switch using differential voltage shaping driver for 13 series li-ion battery cells BMS. ISOCC 2016: 345-346 - 2015
- [j11]Chua-Chin Wang, Deng-Shian Wang, Tzu-Chiao Sung, Yi-Jie Hsieh, Tzung-Je Lee:
A ±3.07% frequency variation clock generator implemented using HV CMOS process. Microelectron. J. 46(4): 285-290 (2015) - 2014
- [j10]Tzung-Je Lee:
9.9 V ASK Demodulator Using Differential Shaper for High-Impedance Electrode. Circuits Syst. Signal Process. 33(7): 2027-2042 (2014) - [c8]Tzung-Je Lee, Kai-Wei Ruan, Chua-Chin Wang:
32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation. ICICDT 2014: 1-4 - 2012
- [c7]Tzung-Je Lee, Wen-Je Lu, Wei-Chih Hsiao, Chua-Chin Wang:
Linear programmable gain amplifier using reconfiguration local-feedback transconductors. APCCAS 2012: 228-231 - [c6]Tzung-Je Lee, Doron Shmilovitz, Yi-Jie Hsieh, Chua-Chin Wang:
Temperature and process compensated clock generator using feedback TPC bias. ICICDT 2012: 1-4 - 2010
- [j9]Chi-Chun Huang, Tzung-Je Lee, Wei-Chih Chang, Chua-Chin Wang:
(1/3) times hboxVDD-to- (3/2) times hboxVDD Wide-Range I/O Buffer Using 0.35- muhboxm 3.3-V CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 57-II(2): 126-130 (2010)
2000 – 2009
- 2009
- [j8]Tzung-Je Lee, Tieh-Yen Chang, Chua-Chin Wang:
Wide-Range 5.0/3.3/1.8-V I/O Buffer Using 0.35-m 3.3-V CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(4): 763-772 (2009) - 2008
- [j7]Chua-Chin Wang, Tzung-Je Lee, U. Fat Chio, Yu-Tzu Hsiao, Jia-Jin Chen:
A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants. Microelectron. J. 39(1): 130-136 (2008) - [j6]Tzung-Je Lee, Ching-Li Lee, Yan-Jhin Ciou, Chi-Chun Huang, Chua-Chin Wang:
All-MOS ASK Demodulator for Low-Frequency Applications. IEEE Trans. Circuits Syst. II Express Briefs 55-II(5): 474-478 (2008) - [j5]Tzung-Je Lee, Chua-Chin Wang:
A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators. VLSI Design 2008: 512946:1-512946:8 (2008) - [c5]Tzung-Je Lee, Wei-Chih Chang, Chua-Chin Wang:
Mixed-voltage I/O buffer using 0.35 μm CMOS technology. ICECS 2008: 850-853 - 2007
- [j4]Chua-Chin Wang, Tzung-Je Lee, Chih-Chen Li, Ron Hu:
Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator. Microelectron. J. 38(2): 197-202 (2007) - 2006
- [j3]Chua-Chin Wang, Tzung-Je Lee, Chih-Chen Li, Ron Hu:
An All-MOS High-Linearity Voltage-to-Frequency Converter Chip With 520-kHz/V Sensitivity. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 744-747 (2006) - [j2]Chua-Chin Wang, Tzung-Je Lee, Hoi Kam Lo, Shih-Ping Lin, Ron Hu:
High-sensitivity and high-mobility compact DVB-T receiver for in-car entertainment. IEEE Trans. Consumer Electron. 52(1): 21-25 (2006) - [c4]Chua-Chin Wang, Tzung-Je Lee, Chih-Chen Li, Ron Hu:
An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V Sensitivity. APCCAS 2006: 267-270 - [c3]Chua-Chin Wang, Chi-Chun Huang, Tzung-Je Lee, Cheng-Mu Wu, Gang-Neng Sung, Kuan-Wen Fang, Sheng-Lun Tseng, Jia-Jin Chen:
An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording. APCCAS 2006: 682-685 - [c2]Chua-Chin Wang, Chi-Chun Huang, Tzung-Je Lee, U. Fat Chio:
A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR. APCCAS 2006: 880-883 - 2005
- [j1]Chua-Chin Wang, Tzung-Je Lee, Yu-Tzu Hsiao, U. Fat Chio, Chi-Chun Huang, J.-J. J. Chin, Ya-Hsin Hsueh:
A multiparameter implantable microstimulator SOC. IEEE Trans. Very Large Scale Integr. Syst. 13(12): 1399-1402 (2005) - 2004
- [c1]Chua-Chin Wang, Yih-Long Tseng, Tzung-Je Lee, Ron Hu:
High-PSR bias circuitry for NTSC sync separation. ISCAS (1) 2004: 329-332
Coauthor Index
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