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Josep Maria Insenser
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2000 – 2009
- 2001
- [j1]E. Cantó, Juan Manuel Moreno, Joan Cabestany
, Ignacio Lacadena, Josep Maria Insenser:
A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 210-218 (2001) - 2000
- [c8]E. Cantó, Juan Manuel Moreno, Joan Cabestany, Ignacio Lacadena, Josep Maria Insenser:
Implementation of Virtual Circuits by Means of the FIPSOC Devices. FPL 2000: 87-95
1990 – 1999
- 1999
- [c7]Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany
Realization of Self-Repairing and Evolvable Hardware Structures by Means of Implicit Self-Configuration. Evolvable Hardware 1999: 182-187 - [c6]E. Cantó, Juan Manuel Moreno, Joan Cabestany, Julio Faura, Josep Maria Insenser:
A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic. FPL 1999: 134-143 - [c5]Juan Manuel Moreno, Joan Cabestany
The Role of Dynamic Reconfiguration for Implementing Artificial Neural Networks Models in Programmable Hardware. IWANN (2) 1999: 85-94 - 1998
- [c4]Julio Faura, Ignacio Lacadena, Antonio Torralba, Josep Maria Insenser:
Programmable analog hardware: a case study. ICECS 1998: 297-300 - [c3]Juan Manuel Moreno, Jordi Madrenas
Feasible Evolutionary and Self-Repairing Hardware by Means of the Dynamic Reconfiguration Capabilities of the FIPSOC Devices. ICES 1998: 345-355 - 1997
- [c2]Julio Faura, C. Horton, B. Krah, Joan Cabestany, M. A. Aguirre, Josep Maria Insenser:
A new field programmable system-on-a-chip for mixed signal integration. ED&TC 1997: 610 - [c1]Julio Faura, Juan Manuel Moreno, Miguel Angel Aguirre Echánove, Phuoc van Duong, Josep Maria Insenser:
Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor. FPL 1997: 1-10
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