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Michel Dubois 0001
Person information
- affiliation: University of Southern California, Los Angeles, CA, USA
Other persons with the same name
- Michel Dubois — disambiguation page
- Michel Dubois 0002 — Univ. Grenoble Alpes, Grenoble, France
- Michel Dubois 0003
— La Poste, Cybersecurity Department, Paris, France (and 1 more)
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2020 – today
- 2020
- [c70]Sang Wook Stephen Do, Michel Dubois:
Transaction-Based Core Reliability. IPDPS 2020: 168-179
2010 – 2019
- 2018
- [j53]Sang Wook Stephen Do, Michel Dubois:
Core Reliability: Leveraging Hardware Transactional Memory. IEEE Comput. Archit. Lett. 17(2): 105-108 (2018) - 2016
- [j52]Sang Wook Stephen Do, Michel Dubois:
Power Efficient Hardware Transactional Memory: Dynamic Issue of Transactions. ACM Trans. Archit. Code Optim. 13(1): 9:1-9:25 (2016) - [j51]Mehrtash Manoochehri, Michel Dubois:
Accurate Model for Application Failure Due to Transient Faults in Caches. IEEE Trans. Computers 65(8): 2397-2410 (2016) - 2015
- [j50]Jinho Suh, Chieh-Ting Huang, Michel Dubois:
Dynamic MIPS Rate Stabilization for Complex Processors. ACM Trans. Archit. Code Optim. 12(1): 4:1-4:25 (2015) - [c69]Mehrtash Manoochehri, Michel Dubois:
Chip-independent Error Correction in main memories. SAMOS 2015: 181-188 - 2014
- [j49]Mehrtash Manoochehri, Murali Annavaram
Extremely Low Cost Error Protection with Correctable Parity Protected Cache. IEEE Trans. Computers 63(10): 2431-2444 (2014) - [c68]Waleed Dweik, Murali Annavaram, Michel Dubois:
Reliability-Aware Exceptions: Tolerating intermittent faults in microprocessor array structures. DATE 2014: 1-6 - 2013
- [c67]Jinho Suh, Murali Annavaram
PHYS: Profiled-HYbrid Sampling for soft error reliability benchmarking. DSN 2013: 1-12 - 2012
- [c66]Jinho Suh, Murali Annavaram
MACAU: A Markov model for reliability evaluations of caches under Single-bit and Multi-bit Upsets. HPCA 2012: 3-14 - 2011
- [c65]Mehrtash Manoochehri, Murali Annavaram
CPPC: correctable parity protected cache. ISCA 2011: 223-234 - [c64]Jinho Suh, Mehrtash Manoochehri, Murali Annavaram
Soft error benchmarking of L2 caches with PARMA. SIGMETRICS 2011: 85-96 - 2010
- [c63]Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong
Adaptive and Speculative Slack Simulations of CMPs on CMPs. MICRO 2010: 523-534
2000 – 2009
- 2009
- [j48]Adrian Moga, Michel Dubois:
A comparative evaluation of hybrid distributed shared-memory systems. J. Syst. Archit. 55(1): 43-52 (2009) - [j47]Jianwei Chen, Murali Annavaram, Michel Dubois:
SlackSim: a platform for parallel simulations of CMPs on CMPs. SIGARCH Comput. Archit. News 37(2): 20-29 (2009) - [j46]Jianwei Chen, Murali Annavaram
SlackSim: a platform for parallel simulations of CMPs on CMPs. SIGMETRICS Perform. Evaluation Rev. 37(2): 77-78 (2009) - [j45]Woojin Choi, Seok-Jun Park, Michel Dubois:
Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors. Trans. High Perform. Embed. Archit. Compil. 2: 107-127 (2009) - [c62]Jianwei Chen, Murali Annavaram
Exploiting Simulation Slack to Improve Parallel Simulation Speed. ICPP 2009: 371-378 - [c61]Jinho Suh, Michel Dubois:
Dynamic MIPS rate stabilization in out-of-order processors. ISCA 2009: 46-56 - 2008
- [j44]Jaeheon Jeong, Per Stenström, Michel Dubois:
Simple Penalty-Sensitive Cache Replacement Policies. J. Instr. Level Parallelism 10 (2008) - [j43]Xiaogang Qiu, Michel Dubois:
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches. IEEE Trans. Computers 57(12): 1585-1599 (2008) - [c60]Michel Dubois, Hyunyoung Lee:
STAMP: A universal algorithmic model for next-generation multithreaded machines and systems. IPDPS 2008: 1-5 - [e3]Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer:
High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings. Lecture Notes in Computer Science 4917, Springer 2008, ISBN 978-3-540-77559-1 [contents] - 2007
- [j42]Jianwei Chen, Michel Dubois, Per Stenström:
SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators. IEEE Micro 27(4): 34-48 (2007) - [c59]Md. Mafijul Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenström:
Loop-level Speculative Parallelism in Embedded Applications. ICPP 2007: 3 - [c58]Michel Dubois, Hyunyoung Lee, Lan Lin:
STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems. IPDPS 2007: 1-8 - [e2]Utpal Banerjee, José Moreira, Michel Dubois, Per Stenström:
Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007. ACM 2007, ISBN 978-1-59593-683-7 [contents] - 2006
- [j41]Jaeheon Jeong, Michel Dubois:
Cache Replacement Algorithms with Nonuniform Miss Costs. IEEE Trans. Computers 55(4): 353-365 (2006) - [c57]Jaeheon Jeong, Per Stenström, Michel Dubois:
Simple penalty-sensitive replacement policies for caches. Conf. Computing Frontiers 2006: 341-352 - [e1]Laxmi N. Bhuyan, Michel Dubois, Will Eatherton:
Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2006, San Jose, California, USA, December 3-5, 2006. ACM 2006, ISBN 1-59593-580-0 [contents] - 2005
- [j40]Xiaogang Qiu, Michel Dubois:
Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. 16(7): 612-623 (2005) - [c56]Nasir Mohyuddin, Rashed Zafar Bhatti, Michel Dubois:
Controlling leakage power with the replacement policy in slumberous caches. Conf. Computing Frontiers 2005: 161-170 - 2004
- [j39]Xiaogang Qiu, Michel Dubois:
Tolerating Late Memory Traps in Dynamically Scheduled Processors. IEEE Trans. Computers 53(6): 732-743 (2004) - [c55]Michel Dubois:
Fighting the memory wall with assisted execution. Conf. Computing Frontiers 2004: 168-180 - [c54]Martin Kämpe, Per Stenström, Michel Dubois:
Self-correcting LRU replacement policies. Conf. Computing Frontiers 2004: 181-191 - 2003
- [j38]Adrian Moga, Michel Dubois:
Scalability implications of software-implemented coherence. Comput. Syst. Sci. Eng. 18(1): 7-15 (2003) - [c53]Jaeheon Jeong, Michel Dubois:
Cost-Sensitive Cache Replacement Algorithms. HPCA 2003: 327-337 - [c52]Jianwei Chen, Michel Dubois, Per Stenström:
Integrating complete-system and user-level performance/power simulators: the SimWattch approach. ISPASS 2003: 1-10 - 2002
- [j37]Michel Dubois, Jaeheon Jeong, Ashwini K. Nanda:
Shared cache architectures for decision support systems. Perform. Evaluation 49(1/4): 283-298 (2002) - [c51]Martin Kämpe, Per Stenström, Michel Dubois:
The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches. HPCA 2002: 223-232 - 2001
- [c50]Xiaogang Qiu, Michel Dubois:
Towards Virtually-Addressed Memory Hierarchies. HPCA 2001: 51-62 - 2000
- [j36]Jonas Skeppstedt, Michel Dubois:
Compiler Controlled Prefetching for Multiprocessors Using Low-Overhead Traps and Prefetch Engines. J. Parallel Distributed Comput. 60(5): 585-615 (2000) - [j35]Fong Pong, Michel Dubois:
Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models. IEEE Trans. Parallel Distributed Syst. 11(9): 989-1006 (2000)
1990 – 1999
- 1999
- [c49]Xiaogang Qiu, Michel Dubois:
Tolerating Late Memory Traps in ILP Processors. ISCA 1999: 76-87 - [c48]Jaeheon Jeong, Michel Dubois:
Optimal Replacements in Caches with Two Miss Costs. SPAA 1999: 155-164 - 1998
- [j34]Michel Dubois, Jaeheon Jeong, Yong Ho Song, Adrian Moga:
Rapid Hardware Prototyping on RPM-2. IEEE Des. Test Comput. 15(3): 112-118 (1998) - [j33]Fong Pong, Michel Dubois:
Formal Verification of Complex Coherence Protocols Using Symbolic State Models. J. ACM 45(4): 557-587 (1998) - [j32]Kangwoo Lee, Michel Dubois:
Empirical Models of Miss Rates. Parallel Comput. 24(2): 205-219 (1998) - [j31]Fong Pong, Michael C. Browne, Gunes Aybay, Andreas Nowatzyk, Michel Dubois:
Design Verification of the S3.mp Cache-Coherent Shared-Memory System. IEEE Trans. Computers 47(1): 135-140 (1998) - [j30]Fredrik Dahlgren, Michel Dubois, Per Stenström:
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. IEEE Trans. Computers 47(10): 1041-1055 (1998) - [c47]Adrian Moga, Michel Dubois:
The Effectiveness of SRAM Network Caches in Clustered DSMs. HPCA 1998: 103-112 - [c46]Michel Dubois, Christoph Scheurich:
Retrospective: Memory Access Buffering in Multiprocessors. 25 Years ISCA: Retrospectives and Reprints 1998: 48-50 - [c45]Xiaogang Qiu, Michel Dubois:
Options for Dynamic Address Translation in COMAs. ISCA 1998: 214-225 - [c44]Michel Dubois, Christoph Scheurich, Faye A. Briggs:
Memory Access Buffering in Multiprocessors. 25 Years ISCA: Retrospectives and Reprints 1998: 320-328 - [c43]Christopher Ho, Heidi E. Ziegler, Michel Dubois:
In-Memory Directories: Eliminating the Cost of Directories in CC-NUMAs. SPAA 1998: 222-230 - 1997
- [j29]Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn
Boosting the Performance of Shared Memory Multiprocessors. Computer 30(7): 63-70 (1997) - [j28]Fong Pong, Michel Dubois:
Verification Techniques for Cache Coherence Protocols. ACM Comput. Surv. 29(1): 82-126 (1997) - [j27]Michel Cekleov, Michel Dubois:
Virtual-address caches. Part 1: problems and solutions in uniprocessors. IEEE Micro 17(5): 64-71 (1997) - [j26]Michel Cekleov, Michel Dubois:
Virtual-address caches.2. Multiprocessor issues. IEEE Micro 17(6): 69-74 (1997) - [c42]Kangwoo Lee, Woo-Jong Han, Michel Dubois:
Bottleneck-Free Interconnect and IO Subsystem in SPAX. ICPADS 1997: 524-533 - [c41]Adrian Moga, Michel Dubois, Alain Gefflaut:
Hardware Versus Software Implementation of COMA. ICPP 1997: 248-256 - [c40]Jonas Skeppstedt, Michel Dubois:
Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps. ICPP 1997: 298-305 - 1996
- [j25]Aydin Üresin, Michel Dubois:
Effects of Asynchronism on the Convergence Rate of Iterative Algorithms. J. Parallel Distributed Comput. 34(1): 66-81 (1996) - [c39]Fong Pong, Michel Dubois:
Formal Verification of Delayed Consistency Protocols. IPPS 1996: 124-131 - [c38]Adrian Moga, Michel Dubois:
Performance of Asynchronous Linear Iterations with Random Delays. IPPS 1996: 625-629 - 1995
- [j24]Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Koray Öner, Michel Dubois:
RPM: A Rapid Prototyping Engine for Multiprocessor Systems. Computer 28(2): 26-34 (1995) - [j23]Håkan Grahn
Implementation and evaluation of update-based cache protocols under relaxed memory consistency models. Future Gener. Comput. Syst. 11(3): 247-271 (1995) - [j22]Michel Dubois, Jonas Skeppstedt, Per Stenström:
Essential Misses and Data Traffic in Coherence Protocols. J. Parallel Distributed Comput. 29(2): 108-125 (1995) - [j21]Luiz André Barroso, Michel Dubois:
Performance Evaluation of the Slotted Ring Multiprocessor. IEEE Trans. Computers 44(7): 878-890 (1995) - [j20]Fredrik Dahlgren, Michel Dubois, Per Stenström:
Sequential Hardware Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. 6(7): 733-746 (1995) - [j19]Fong Pong, Michel Dubois:
A New Approach for the Verification of Cache Coherence Protocols. IEEE Trans. Parallel Distributed Syst. 6(8): 773-787 (1995) - [c37]Fong Pong, Andreas Nowatzyk, Gunes Aybay, Michel Dubois:
Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study. Euro-Par 1995: 287-300 - [c36]Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois:
The Design of RPM: An FPGA-based Multiprocessor Emulator. FPGA 1995: 60-66 - 1994
- [c35]Fong Pong, Per Stenström, Michel Dubois:
An Integrated Methodology for the Verification of Directory-Based Cache Protocols. ICPP (1) 1994: 158-165 - [c34]Fredrik Dahlgren, Michel Dubois, Per Stenström:
Combined Performance Gains of Simple Cache Protocol Extensions. ISCA 1994: 187-197 - 1993
- [c33]Fredrik Dahlgren, Michel Dubois, Per Stenström:
Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. ICPP (1) 1993: 56-63 - [c32]Koray Öner, Michel Dubois:
Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures. International Conference on Supercomputing 1993: 338-347 - [c31]Yung-Syau Chen, Michel Dubois:
Cache Protocols with Partial Block Invalidations. IPPS 1993: 16-23 - [c30]Michel Dubois, Jonas Skeppstedt, Livio Ricciulli, Krishnan Ramamurthy, Per Stenström:
The Detection and Elimination of Useless Misses in Multiprocessors. ISCA 1993: 88-97 - [c29]Luiz André Barroso, Michel Dubois:
The Performance of Cache-Coherent Ring-based Multiprocessors. ISCA 1993: 268-277 - [c28]Jacqueline Chame, Michel Dubois:
Cache Inclusion and Processor Sampling in Multiprocessor Simulations. SIGMETRICS 1993: 36-47 - [c27]Fong Pong, Michel Dubois:
The Verification of Cache Coherence Protocols. SPAA 1993: 11-20 - [c26]Fong Pong, Michel Dubois:
Correctness of a Directory-Based Cache Coherence Protocol: Early Experience. SPDP 1993: 37-44 - 1992
- [j18]Michel Dubois:
Special Issue on Memory System Architectures for Scalable Multiprocessors. J. Parallel Distributed Comput. 15(4): 303-304 (1992) - [c25]Ashfaq A. Khokhar, Michel Dubois:
Matching Algorithms and Architecture in Hierarchical Shared-Memory Multiprocessor (HMS) Systems. IPPS 1992: 558-561 - [c24]Michel Dubois, Luiz André Barroso, Yung-Syau Chen, Koray Öner:
Scalability Problems in Multiprocessors with Private Caches. PARLE 1992: 211-230 - 1991
- [j17]Christoph Scheurich, Michel Dubois:
Lockup-free Caches in High-Performance Multiprocessors. J. Parallel Distributed Comput. 11(1): 25-36 (1991) - [j16]Michel Dubois, Jin-Chin Wang:
Shared Block Contention in a Cache Coherence Protocol. IEEE Trans. Computers 40(5): 640-644 (1991) - [j15]Michel Dubois, Faye A. Briggs:
The Run-Time Efficiency of Parallel Asynchronous Algorithms. IEEE Trans. Computers 40(11): 1260-1266 (1991) - [c23]Luiz André Barroso, Michel Dubois:
Cache Coherence on a Slotted Ring. ICPP (1) 1991: 230-237 - [c22]Jin-Chin Wang, Michel Dubois, Faye A. Briggs:
Analytical Modeling for Finite Cache Effects. ICPP (1) 1991: 287-291 - [c21]Michel Dubois, Jin-Chin Wang, Luiz André Barroso, Kangwoo Lee, Yung-Syau Chen:
Delayed consistency and its effects on the miss rate of parallel programs. SC 1991: 197-206 - 1990
- [j14]Michel Dubois, Shreekant S. Thakkar:
Cache Architectures in Tightly Coupled Multiprocessors - Guest Editors' Introduction to the Special Issue. Computer 23(6): 9-11 (1990) - [j13]Shreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, Alvin M. Despain:
Scalable Shared-Memory Multiprocessor Architectures. Computer 23(6): 71-83 (1990) - [j12]Jin-Chin Wang, Michel Dubois:
Performance comparison of cache coherence protocols based on the access burst model. Comput. Syst. Sci. Eng. 5(3): 147-158 (1990) - [j11]Aydin Üresin, Michel Dubois:
Parallel Asynchronous Algorithms for Discrete Data. J. ACM 37(3): 588-606 (1990) - [j10]Michel Dubois, Christoph Scheurich:
Memory Access Dependencies in Shared-Memory Multiprocessors. IEEE Trans. Software Eng. 16(6): 660-673 (1990) - [c20]Anastasios A. Economides, Michel Dubois:
Transient Models of Bus-Based Multiprocessors. ICPP (1) 1990: 153-160 - [c19]Aydin Üresin, Michel Dubois:
Asynchronous Iterations with Bounded Delay. ICPP (3) 1990: 236-243 - [c18]Sharad Mehrotra, Chien-Ming Cheng, Kai Hwang, Michel Dubois, Dhabaleswar K. Panda:
Algorithm-Driven Simulation and Performance Projection of a RISC-based Orthogonal Multiprocessor. ICPP (3) 1990: 244-253 - [c17]Kai Hwang, Michel Dubois, Dhabaleswar K. Panda, S. Rao, Shisheng Shang, Aydin Üresin, W. Mao, H. Nair, M. Lytwyn, F. Hsieh, J. Liu, Sharad Mehrotra, Chien-Ming Cheng:
OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses. ICS 1990: 7-22
1980 – 1989
- 1989
- [j9]Aydin Üresin, Michel Dubois:
Sufficient conditions for the convergence of asynchronous iterations. Parallel Comput. 10(1): 83-92 (1989) - [j8]Christoph Scheurich, Michel Dubois:
Dynamic Page Migration in Multiprocessors with Distributed Global Memory. IEEE Trans. Computers 38(8): 1154-1163 (1989) - 1988
- [j7]Michel Dubois, Christoph Scheurich, Faye A. Briggs:
Synchronization, Coherence, and Event Ordering in Multiprocessors. Computer 21(2): 9-21 (1988) - [j6]Michel Dubois:
Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses. IEEE Trans. Computers 37(1): 58-70 (1988) - [c16]Christoph Scheurich, Michel Dubois:
Dynamic Page Migration in Multiprocessors with Distributed Global Memory. ICDCS 1988: 162-169 - [c15]Christoph Scheurich, Michel Dubois:
Concurrent Miss Resolution in Multiprocessor Caches. ICPP (1) 1988: 118-125 - [c14]Michel Dubois, Jin-Chin Wang:
Shared Data Contention in a Cache Coherence Protocol. ICPP (1) 1988: 146-155 - [c13]Christoph Scheurich, Michel Dubois:
The design of a lockup-free cache for high-performance multiprocessors. SC 1988: 352-359 - 1987
- [c12]Michel Dubois:
Effect of Invalidations on the Hit Ratio of Cache-Based Multiprocessors. ICPP 1987: 255-257 - [c11]Aydin Üresin, Michel Dubois:
Asynchronous Relaxation of Non-Numerical Data. ICPP 1987: 499-501 - [c10]Christoph Scheurich, Michel Dubois:
Correct Memory Operation of Cache-Based Multiprocessors. ISCA 1987: 234-243 - 1986
- [j5]Jean-Luc Gaudiot, Michel Dubois, Liang-Teh Lee, Nadim G. Tohme:
The TX16: A Highly Programmable Multi-microprocessor Architecture. IEEE Micro 6(5): 18-31 (1986) - [c9]Aydin Üresin, Michel Dubois:
Generalized Asynchronous Iterations. CONPAR 1986: 272-278 - [c8]Michel Dubois, Faye A. Briggs, Indira Patil, Meera Balakrishnan:
Trace-Driven Simulations of Parallel and Distributed Algorithms in Multiprocessors. ICPP 1986: 909-916 - [c7]Michel Dubois, Christoph Scheurich, Faye A. Briggs:
Memory Access Buffering in Multiprocessors. ISCA 1986: 434-442 - 1985
- [j4]Michel Dubois:
A Cache-Based Multiprocessor with High Efficiency. IEEE Trans. Computers 34(10): 968-972 (1985) - [c6]Michel Dubois:
A Cache-Based Multiprocessor with High Efficiency. ICPP 1985: 646-648 - 1983
- [j3]Faye A. Briggs, Michel Dubois:
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories. IEEE Trans. Computers 32(1): 48-59 (1983) - 1982
- [j2]Michel Dubois, Faye A. Briggs:
Effects of Cache Coherency in Multiprocessors. IEEE Trans. Computers 31(11): 1083-1099 (1982) - [j1]Michel Dubois, Faye A. Briggs:
Performance of Synchronized Iterative Processes in Multiprocessor Systems. IEEE Trans. Software Eng. 8(4): 419-431 (1982) - [c5]Michel Dubois, Faye A. Briggs:
An approximate analytical model for asynchronous processes in multiprocessors. ICPP 1982: 290-297 - [c4]Michel Dubois, Faye A. Briggs:
Effects of cache coherency in multiprocessors. ISCA 1982: 299-308 - 1981
- [c3]Faye A. Briggs, Michel Dubois, Kai Hwang:
Throughout Analysis and Configuration Design of a Shared-Resource Multiprocessor System: PUMPS. ISCA 1981: 67-80 - [c2]Michel Dubois, Faye A. Briggs:
Efficient Interprocessor Communications for MIMD Multiprocessor Systems. ISCA 1981: 187-196 - [c1]Faye A. Briggs, Michel Dubois:
Performance of Cache-Based Multiprocessors. SIGMETRICS 1981: 181-190
Coauthor Index
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