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Bao Liu 0001
Person information
- affiliation: University of Texas, San Antonio, TX, USA
- affiliation (PhD 2003): University of California San Diego, La Jolla, CA, USA
Other persons with the same name
- Bao Liu — disambiguation page
- Bao Liu 0002
— Southeast University, Nanjing, China (and 1 more)
- Bao Liu 0003
- Bao Liu 0004
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2010 – 2019
- 2015
- [j14]Bao Liu, Brandon Wang:
Reconfiguration-Based VLSI Design for Security. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 98-108 (2015) - [j13]Vivek K. De, Andrew B. Kahng, Tanay Karnik, Bao Liu, Milad Maleki, Lu Wang:
Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design. ACM J. Emerg. Technol. Comput. Syst. 12(3): 21:1-21:19 (2015) - [j12]Bao Liu, Lu Wang:
Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1577-1590 (2015) - [c35]Yao Chen, Andrew B. Kahng, Bao Liu, Wenjun Wang:
Crosstalk-aware signal probability-based dynamic statistical timing analysis. ISQED 2015: 424-429 - 2014
- [c34]Bao Liu, Brandon Wang:
Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks. DATE 2014: 1-6 - [c33]Bao Liu, Chiung-Hung Chen:
Testing, diagnosis and repair methods for NBTI-induced SRAM faults. ICICDT 2014: 1-4 - [c32]Bao Liu:
Input-aware statistical timing analysis for VLSI delay test and average design. MWSCAS 2014: 1005-1008 - [c31]Lu Wang, Xutao Wang, Milad Maleki, Bao Liu:
Power/ground supply voltage variation-aware delay test pattern generation. VTS 2014: 1-6 - 2013
- [c30]Bao Liu, Lu Wang:
Input-aware statistical timing analysis-based delay test pattern generation. ISQED 2013: 454-459 - [c29]Bao Liu, Lu Wang, Juan Portillo:
Variable latency VLSI design based on timing analysis, delay ATPG, and completion prediction. MWSCAS 2013: 653-656 - 2012
- [j11]Bao Liu, Xuemei Chen, Fiona Teshome:
Resilient and adaptive performance logic. ACM J. Emerg. Technol. Comput. Syst. 8(3): 22:1-22:16 (2012) - [c28]Bao Liu, Lu Wang:
Minimum logic of guaranteed single soft error resilience based on group distance-two code. ICICDT 2012: 1-4 - [c27]Bao Liu, Xuemei Chen, Fiona Teshome:
Delay insensitive code-based timing and soft error-resilient and adaptive-performance logic. ISQED 2012: 63-72 - 2011
- [c26]Zhigang Hao, Ruijing Shen, Sheldon X.-D. Tan, Bao Liu, Guoyong Shi, Yici Cai:
Statistical full-chip dynamic power estimation considering spatial correlations. ISQED 2011: 677-682 - 2010
- [j10]Bao Liu:
Voltage-controlled nano-addressing for nanosystem communication. Nano Commun. Networks 1(3): 224-231 (2010) - [j9]Bao Liu:
Architecture exploration of crossbar-based nanoscale reconfigurable computing platforms. Nano Commun. Networks 1(3): 232-241 (2010) - [c25]Bao Liu:
Error-detecting/correcting-code-based self-checked/corrected/timed circuits. AHS 2010: 66-72
2000 – 2009
- 2009
- [j8]Khader Mohammad
Reduced Voltage Scaling in Clock Distribution Networks. VLSI Design 2009: 679853:1-679853:7 (2009) - [c24]Bao Liu:
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture. ASP-DAC 2009: 853-858 - [c23]Bao Liu:
Analysis and extraction of parametric variation effects on microelectrofluidics-based biochips. BMAS 2009: 60-65 - [c22]Bao Liu:
Defect Mapping and Adaptive Configuration of Nanoelectronic Circuits Based on a CNT Crossbar Nano-Architecture. ICCCN 2009: 1-6 - [c21]Bao Liu:
Robust differential asynchronous nanoelectronic circuits. ISQED 2009: 97-102 - [c20]Bao Liu:
Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution. ISQED 2009: 430-435 - [c19]Khader Mohammad
Energy Efficient Swing signal generation circuits for clock distribution networks. SMC 2009: 3495-3498 - 2008
- [c18]Bao Liu:
Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression. DATE 2008: 527-532 - [c17]Bao Liu:
Signal Probability Based Statistical Timing Analysis. DATE 2008: 562-567 - [c16]Bao Liu:
A Voltage Controlled Nano Addressing Circuit. NanoNet 2008: 66-68 - 2007
- [j7]Andrew B. Kahng, Bao Liu, Xu Xu:
Statistical Timing Analysis in the Presence of Signal-Integrity Effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1873-1877 (2007) - [j6]Andrew B. Kahng, Bao Liu, Qinke Wang:
Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 904-912 (2007) - [j5]Bao Liu, Sheldon X.-D. Tan:
Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1284-1287 (2007) - [c15]Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman:
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. ASP-DAC 2007: 24-31 - [c14]Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu:
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. ICCD 2007: 71-77 - [c13]Bao Liu:
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations. ISQED 2007: 257-262 - 2006
- [c12]Andrew B. Kahng, Bao Liu, Xu Xu:
Statistical gate delay calculation with crosstalk alignment consideration. ACM Great Lakes Symposium on VLSI 2006: 223-228 - [c11]Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan:
Efficient decoupling capacitor planning via convex programming methods. ISPD 2006: 102-107 - [c10]Andrew B. Kahng, Bao Liu, Xu Xu:
Constructing Current-Based Gate Models Based on Existing Timing Library. ISQED 2006: 37-42 - [c9]Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan:
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. ISQED 2006: 638-643 - [c8]Andrew B. Kahng, Bao Liu, Xu Xu:
Statistical crosstalk aggressor alignment aware interconnect delay calculation. SLIP 2006: 91-97 - 2005
- [c7]Andrew B. Kahng, Bao Liu, Qinke Wang:
Supply Voltage Degradation Aware Analytical Placement. ICCD 2005: 437-443 - 2004
- [j4]Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
Nontree routing for reliability and yield improvement [IC layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 148-156 (2004) - 2003
- [j3]Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
Minimum buffered routing with bounded capacitive load for slew rate and reliability control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 241-253 (2003) - [j2]Christoph Albrecht, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
On the skew-bounded minimum-buffer routing tree problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 937-945 (2003) - [c6]Andrew B. Kahng, Bao Liu:
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization. ISVLSI 2003: 183-188 - 2002
- [j1]Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt:
Toward better wireload models in the presence of obstacles. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 177-189 (2002) - [c5]Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
Non-tree routing for reliability and yield improvement. ICCAD 2002: 260-266 - 2001
- [c4]Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt:
Toward better wireload models in the presence of obstacles. ASP-DAC 2001: 527-532 - [c3]Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. ICCAD 2001: 408- - [c2]Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia:
Buffered Steiner trees for difficult instances. ISPD 2001: 4-9 - [c1]Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu:
Interconnect implications of growth-based structural models for VLSI circuits. SLIP 2001: 99-106
Coauthor Index
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