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Chia-Yu Yao
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2020 – today
- 2024
- [j21]Chia-Yu Yao
, Yu-Zhe Huang
The Design of the NLMS Adaptive Filters Using the Fast-Division Approximation With CSD Encoded Divisors. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2459-2463 (2024) - [c19]Yu-Zhe Huang, Chia-Yu Yao, Ping-Yi Lee:
Speeding up the Throughput of an NLMS Adaptive Filter. ICCE-Taiwan 2024: 221-222 - 2021
- [j20]Bo-Han Kung
An Efficient ECG Classification System Using Resource-Saving Architecture and Random Forest. IEEE J. Biomed. Health Informatics 25(6): 1904-1914 (2021)
2010 – 2019
- 2019
- [c18]Ting-Hui Chang, Chia-Yu Yao:
A 11.75-bit Hybrid Sturdy MASH-21 Δ-Σ Modulator for Audio Applications. ISPACS 2019: 1-2 - 2018
- [c17]Chia-Yu Yao, Wei-Chun Hsia
Controlling a switched beam array antenna using PLL frequency synthesizers based on the congruence modulo. ISCAS 2018: 1-4 - 2017
- [c16]Chia-Yu Yao, Shui-Chin Wang:
A QCQP design method of the symmetric pulse-shaping filters against receiver timing jitter. ISCAS 2017: 1-4 - 2016
- [j19]Wei-Cheng Chen, Chao-Chyun Chen, Chia-Yu Yao, Rong-Jyi Yang:
A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 17-25 (2016) - [j18]Yung-Hsiang Ho, Chia-Yu Yao:
A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 759-763 (2016) - [j17]Yung-Hsiang Ho, Chia-Yu Yao:
A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase-Frequency-Error Compensation. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1984-1992 (2016) - 2015
- [j16]Chia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, Rong-Jyi Yang:
Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 567-574 (2015) - [c15]Chia-Yu Yao, Yung-Hsiang Ho, Wei-Chun Hsia, Jyun-Jie Huang:
Simulating delta-sigma analog-to-digital converters with the Op-Amp nonlinearity using the Newton's method. ISCAS 2015: 537-540 - 2014
- [j15]Chia-Yu Yao, Wei-Chun Hsia, Yung-Hsiang Ho:
Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression Space. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 202-212 (2014) - [j14]Chia-Yu Yao, Wei-Chun Hsia
A -21.2-dBm Dual-Channel UHF Passive CMOS RFID Tag Design. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 1269-1279 (2014) - [j13]Chia-Yu Yao, Wei-Chun Hsia
The Soft-Injection-Locked Ring Oscillator and Its Application in a Vernier-Based TDC. IEEE Trans. Instrum. Meas. 63(8): 2064-2071 (2014) - 2013
- [c14]Yi-Chia Lee, Chia-Yu Yao, Cheng-Yu Hsieh, Jau-Yi Wu, Yi-Hsuan Hsieh, Chien-Hsiung Chen, Rung-Huei Liang
Egg Pair - A hearing game for the visually impaired people using RFID. ISCE 2013: 3-4 - [c13]Ming-Hsien Lee, Chia-Yu Yao, Muhammad Khaerul Naim
Demodulator for multi-carrier UHF RFID tags. ISCE 2013: 5-6 - [c12]Chia-Yu Yao, Yung-Hsiang Ho:
A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism. VLSI-DAT 2013: 1-4 - 2012
- [j12]Chia-Yu Yao:
The Design of Hybrid Asymmetric-FIR/Analog Pulse-Shaping Filters Against Receiver Timing Jitter. IEEE Trans. Commun. 60(5): 1199-1203 (2012) - [j11]Chia-Yu Yao, Alan N. Willson Jr.:
The Design of Hybrid Symmetric-FIR/Analog Pulse-Shaping Filters. IEEE Trans. Signal Process. 60(4): 2060-2065 (2012) - [c11]Wei-Cheng Chen, Rong-Jyi Yang, Chia-Yu Yao, Chao-Chyun Chen:
A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm. ISPACS 2012: 338-342 - [c10]Chia-Yu Yao, Yung-Hsiang Ho, Wei-Chun Hsia:
Optimization of the hybrid asymmetric-FIR/analog square-root filters. ISPACS 2012: 395-400 - 2011
- [c9]Ming-Hsien Lee, Chia-Yu Yao, Hsin-Chin Liu:
Passive Tag for Multi-carrier RFID Systems. ICPADS 2011: 872-876 - 2010
- [c8]Chia-Yu Yao, Chung-Lin Sha:
Fixed-point FIR filter design and implementation in the expanding subexpression space. ISCAS 2010: 185-188
2000 – 2009
- 2009
- [j10]Chia-Yu Yao, Chih-Chun Hsieh:
Hardware Simplification to the Delta Path in a MASH 111 Delta-Sigma Modulator. IEEE Trans. Circuits Syst. II Express Briefs 56-II(4): 270-274 (2009) - 2008
- [j9]Chia-Yu Yao, Chin-Chih Yeh:
An Application of the Second-Order Passive Lead-Lag Loop Filter for Analog PLLs to the Third-Order Charge-Pump PLLs. IEEE Trans. Ind. Electron. 55(2): 972-974 (2008) - [c7]Chia-Yu Yao, Alan N. Willson Jr.:
The design of asymmetrical square-root pulse-shaping filters with wide eye-openings. ISCAS 2008: 2665-2668 - 2007
- [j8]Chia-Yu Yao:
The Design of Square-Root-Raised-Cosine FIR Filters by an Iterative Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(1): 241-248 (2007) - [j7]Chia-Yu Yao, Chun-Te Hsu, Chiang-Ju Chien:
Stability Analysis of Fourth-Order Charge-Pump PLLs Using Linearized Discrete-Time Models. IEICE Trans. Electron. 90-C(3): 628-633 (2007) - [c6]Chia-Yu Yao, Alan N. Willson Jr.:
The Design of Symmetric Square-Root Pulse-Shaping Filters for Transmitters and Receivers. ISCAS 2007: 2056-2059 - 2006
- [c5]Chia-Yu Yao, Chun-Te Hsu, Chin-Chih Yeh:
The Analysis of Phase-jitter Variance in the Third-order CPPLL Frequency Synthesizer. APCCAS 2006: 1043-1046 - 2005
- [c4]Chia-Yu Yao, Chiang-Ju Chien:
Design of a square-root-raised-cosine FIR filter by a recursive method. ISCAS (1) 2005: 512-515 - 2004
- [j6]Chiang-Ju Chien, Chia-Yu Yao:
An output-based adaptive iterative learning controller for high relative degree uncertain linear systems. Autom. 40(1): 145-153 (2004) - [j5]Chiang-Ju Chien, Chia-Yu Yao:
Iterative learning of model reference adaptive controller for uncertain nonlinear systems with only output measurement. Autom. 40(5): 855-864 (2004) - [j4]Chia-Yu Yao, Hsin-Horng Chen, Tsuan-Fan Lin, Chiang-Ju Chien, Chun-Te Hsu:
A novel common-subexpression-elimination method for synthesizing fixed-point FIR filters. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(11): 2215-2221 (2004) - [j3]Chiang-Ju Chien, Chun-Te Hsu, Chia-Yu Yao:
Fuzzy system-based adaptive iterative learning control for nonlinear plants with initial state errors. IEEE Trans. Fuzzy Syst. 12(5): 724-732 (2004) - 2003
- [c3]Chun-Te Hsu, Chiang-Ju Chien, Chia-Yu Yao:
A new algorithm of adaptive iterative learning control for uncertain robotic systems. ICRA 2003: 4130-4135 - [c2]Chia-Yu Yao, Chin-Chih Yeh, Tsuan-Fan Lin, Hsin-Horng Chen, Chiang-Ju Chien:
A design flow for linear-phase fixed-point FIR filters: from the NPRM specifications to a VHDL code. ISCAS (4) 2003: 277-280 - 2002
- [j2]Chia-Yu Yao, Chiang-Ju Chien:
A Partial MILP Algorithm for the Design of Linear Phase FIR Filters with SPT Coefficients. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(10): 2302-2310 (2002) - 2001
- [c1]Chia-Yu Yao:
A study of SPT-term distribution of CSD numbers and its application for designing fixed-point linear phase FIR filters. ISCAS (2) 2001: 301-304
1990 – 1999
- 1999
- [j1]Jiing-Yih Lai, Ji-Liang Doong, Chia-Yu Yao:
Three-dimensional CAD model reconstruction from image data of computer tomography. Int. J. Imaging Syst. Technol. 10(4): 328-338 (1999)
Coauthor Index
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