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Sudarshan K. Srinivasan
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2020 – today
- 2024
- [c27]Benedicto James Sitou Campbell, Sudarshan K. Srinivasan:
Formal Verification For Cyclic Quantum Walk Circuits. ISCAS 2024: 1-5 - 2023
- [j20]Kushal K. Ponugoti
, Sudarshan K. Srinivasan, Nimish Mathure:
Verification of serialising instructions for security against transient execution attacks. IET Comput. Digit. Tech. 17(3-4): 127-140 (2023) - [j19]Arun Govindankutty
Rotational abstractions for verification of quantum Fourier transform circuits. IET Quantum Commun. 4(2): 84-92 (2023) - [c26]Nimish Mathure, Sudarshan K. Srinivasan, Kushal K. Ponugoti
Hardware Mitigation and Verification For Rogue In-Flight Data Load Attacks. ICECS 2023: 1-4 - [i3]Arun Govindankutty, Sudarshan K. Srinivasan, Nimish Mathure:
Rotational Abstractions for Verification of Quantum Fourier Transform Circuits. CoRR abs/2301.00737 (2023) - 2022
- [j18]Nimish Mathure
A Refinement-Based Approach to Spectre Invulnerability Verification. IEEE Access 10: 80949-80957 (2022) - [j17]Kushal K. Ponugoti
Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits. IET Comput. Digit. Tech. 16(5-6): 172-182 (2022) - 2021
- [c25]Kushal K. Ponugoti
Formal Verification Approach to Detect Always-On Denial of Service Trojans in Pipelined Circuits. ICECS 2021: 1-6 - 2020
- [j16]N. Shaukat, Sana Shuja
Improved Efficiency of Object Code Verification Using Statically Abstracted Object Code. Sci. Program. 2020: 6791891:1-6791891:19 (2020) - [c24]Nimish Mathure, Sudarshan K. Srinivasan, Kushal K. Ponugoti
A Formal Verification Approach for Detecting Opcode Trojans. ICECS 2020: 1-4 - [c23]Kushal K. Ponugoti
Hardware Trojan Design and Detection in Asynchronous NCL Circuits. ICECS 2020: 1-4 - [c22]Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith:
Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits. MWSCAS 2020: 21-24 - [c21]Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith:
Formal Verification of Completion-Completeness for NCL Circuits. MWSCAS 2020: 25-28
2010 – 2019
- 2019
- [j15]Ashiq A. Sakib
Formal Modeling and Verification of PCHB Asynchronous Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27(12): 2911-2924 (2019) - [c20]Mousam Hossain, Ashiq A. Sakib
An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits. ISCAS 2019: 1-5 - [i2]Zeyad A. Al-Odat, Sudarshan K. Srinivasan, Eman M. Al-Qtiemat, Sana Shuja:
A Reliable IoT-Based Embedded Health Care System for Diabetic Patients. CoRR abs/1908.06086 (2019) - 2018
- [c19]Ashiq A. Sakib
An Equivalence Verification Methodology for Combinational Asynchronous PCHB Circuits. MWSCAS 2018: 767-770 - [i1]Zeyad A. Al-Odat, Sudarshan K. Srinivasan, Eman Al-qtiemat, Mohana Asha Latha Dubasi, Sana Shuja:
IoT-Based Secure Embedded Scheme for Insulin Pump Data Acquisition and Monitoring. CoRR abs/1812.02357 (2018) - 2017
- [j14]Shaista Jabeen, Sudarshan K. Srinivasan, Sana Shuja:
Formal verification methodology for real-time Field Programmable Gate Array. IET Comput. Digit. Tech. 11(5): 197-203 (2017) - [c18]Ashiq A. Sakib
Formal modeling and verification for pre-charge half buffer gates and circuits. MWSCAS 2017: 519-522 - 2015
- [j13]Shaista Jabeen, Sudarshan K. Srinivasan, Sana Shuja, Mohana Asha Latha Dubasi:
A Formal Verification Methodology for FPGA-Based Stepper Motor Control. IEEE Embed. Syst. Lett. 7(3): 85-88 (2015) - [j12]Sana Shuja, Sudarshan K. Srinivasan, Shaista Jabeen, Dharmakeerthi Nawarathna:
A Formal Verification Methodology for DDD Mode Pacemaker Control Programs. J. Electr. Comput. Eng. 2015: 939028:1-939028:10 (2015) - 2014
- [c17]Vidura Wijayasekara, Sudarshan K. Srinivasan, Scott C. Smith:
Equivalence verification for NULL Convention Logic (NCL) circuits. ICCD 2014: 195-201 - [c16]Mohana Asha Latha Dubasi, Sudarshan K. Srinivasan, Vidura Wijayasekara:
Timed Refinement for Verification of Real-Time Object Code Programs. VSTTE 2014: 252-269 - 2013
- [j11]Saif Ur Rehman Malik
Modeling and Analysis of State-of-the-art VM-based Cloud Management Platforms. IEEE Trans. Cloud Comput. 1(1) (2013) - [c15]Vidura Wijaysekara, Sudarshan K. Srinivasan:
Equivalence checking for synchronous elastic circuits. MEMOCODE 2013: 109-118 - 2012
- [j10]Sudarshan K. Srinivasan, Y. Cai, Koushik Sarker:
Refinement-based verification of elastic pipelined systems. IET Comput. Digit. Tech. 6(2): 136-152 (2012) - 2011
- [j9]Raj S. Katti, Sudarshan K. Srinivasan, Aida Vosoughi:
On the Security of Randomized Arithmetic Codes Against Ciphertext-Only Attacks. IEEE Trans. Inf. Forensics Secur. 6(1): 19-27 (2011) - [c14]Sudarshan K. Srinivasan, Raj S. Katti:
Desynchronization: design for verification. FMCAD 2011: 215-222 - 2010
- [j8]Sudarshan K. Srinivasan:
Optimization Techniques for Verification of Out-of-Order Execution Machines. J. Electr. Comput. Eng. 2010: 515021:1-515021:7 (2010) - [j7]Sudarshan K. Srinivasan:
Automatic Refinement Checking of Pipelines with Out-of-Order Execution. IEEE Trans. Computers 59(8): 1138-1144 (2010) - [c13]Rajesh Kavasseri
Joint optimal placement of PMU and conventional measurements in power systems. ISCAS 2010: 3449-3452 - [p1]Panagiotis Manolios
Verifying Pipelines with BAT. Design and Verification of Microprocessor Systems for High-Assurance Applications 2010: 145-174
2000 – 2009
- 2009
- [j6]Sudarshan K. Srinivasan, Koushik Sarker, Rajendra S. Katti:
Verification of Synchronous Elastic Processors. IEEE Embed. Syst. Lett. 1(1): 14-18 (2009) - [j5]Sudarshan K. Srinivasan, Koushik Sarker, Rajendra S. Katti:
Token-Aware Completion Functions for Elastic Processor Verification. J. Electr. Comput. Eng. 2009: 480740:1-480740:5 (2009) - [c12]Raj S. Katti, Sudarshan K. Srinivasan:
Efficient Hardware Implementation of a New Pseudo-random Bit Sequence Generator. ISCAS 2009: 1393-1396 - [c11]Sudarshan K. Srinivasan, Raj S. Katti:
Verification of Desynchronized Circuits. ISCAS 2009: 1509-1512 - 2008
- [j4]Panagiotis Manolios
Automatic verification of safety and liveness for pipelined machines using WEB refinement. ACM Trans. Design Autom. Electr. Syst. 13(3): 45:1-45:19 (2008) - [j3]Panagiotis Manolios
A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 353-364 (2008) - 2007
- [b1]Sudarshan K. Srinivasan:
Efficient Verification of Bit-Level Pipelined Machines Using Refinement. Georgia Institute of Technology, Atlanta, GA, USA, 2007 - [c10]Panagiotis Manolios
BAT: The Bit-Level Analysis Tool. CAV 2007: 303-306 - 2006
- [j2]Panagiotis Manolios
A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures. J. Autom. Reason. 37(1-2): 93-116 (2006) - [c9]Roma Kane, Panagiotis Manolios
Monolithic verification of deep pipelines with collapsed flushing. DATE 2006: 1234-1239 - [c8]Panagiotis Manolios
Automatic memory reductions for RTL model verification. ICCAD 2006: 786-793 - 2005
- [c7]Panagiotis Manolios
A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems. CHARME 2005: 363-366 - [c6]Panagiotis Manolios
Refinement Maps for Efficient Verification of Processor Models. DATE 2005: 1304-1309 - [c5]Panagiotis Manolios
Verification of executable pipelined machines with bit-level interfaces. ICCAD 2005: 855-862 - [c4]Panagiotis Manolios
A complete compositional reasoning framework for the efficient verification of pipelined machines. ICCAD 2005: 863-870 - [c3]Panagiotis Manolios
A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines. MEMOCODE 2005: 188-197 - 2004
- [c2]Panagiotis Manolios
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements. DATE 2004: 168-175 - 2003
- [j1]Jun-Cheol Park, Vincent John Mooney III, Sudarshan K. Srinivasan:
Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems. Microelectron. J. 34(11): 1019-1024 (2003) - [c1]Sudarshan K. Srinivasan, Miroslav N. Velev
Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions. MEMOCODE 2003: 65-74
Coauthor Index
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