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Azadeh Davoodi
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- affiliation: University of Wisconsin, USA
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2020 – today
- 2024
- [c67]Lizi Zhang
, Azadeh Davoodi
Efficient and Effective Neural Networks for Automatic Test Pattern Generation. MLCAD 2024: 1:1-1:7 - [c66]Robert Viramontes
DIME: Distributed Inference Model Estimation for Minimizing Profiled Latency. SMARTCOMP 2024: 356-361 - [i6]Lizi Zhang, Azadeh Davoodi:
Static IR Drop Prediction with Attention U-Net and Saliency-Based Explainability. CoRR abs/2408.03292 (2024) - 2023
- [j34]Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu:
ObfusX: Routing obfuscation with explanatory analysis of a machine learning attack. Integr. 89: 47-55 (2023) - [j33]Oliver Sinnen, Qiang Liu, Azadeh Davoodi:
Introduction to Special Section on FPT'20. ACM Trans. Reconfigurable Technol. Syst. 16(1): 1:1-1:2 (2023) - [c65]Robert Viramontes
Neural Network Partitioning for Fast Distributed Inference. ISQED 2023: 1-7 - [i5]Cheng-En Wu, Azadeh Davoodi, Yu Hen Hu:
Block Pruning for Enhanced Efficiency in Convolutional Neural Networks. CoRR abs/2312.16904 (2023) - 2022
- [j32]Maedeh Hemmat, Joshua San Miguel
CAP'NN: A Class-aware Framework for Personalized Neural Network Inference. ACM Trans. Embed. Comput. Syst. 21(5): 59:1-59:24 (2022) - [c64]Maedeh Hemmat, Azadeh Davoodi, Yu Hen Hu:
$\text{Edge}^{n}$ AI: Distributed Inference with Local Edge Devices and Minimal Latency. ASP-DAC 2022: 544-549 - 2021
- [j31]Boyu Zhang
A Mixture of Experts Approach for Low-Cost DNN Customization. IEEE Des. Test 38(4): 52-59 (2021) - [j30]Maedeh Hemmat
AirNN: A Featherweight Framework for Dynamic Input-Dependent Approximation of CNNs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2090-2103 (2021) - [c63]Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu
ObfusX: Routing Obfuscation with Explanatory Analysis of a Machine Learning Attack. ASP-DAC 2021: 548-554 - [c62]Shubham Rai
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - [c61]Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu
Sampling-Based Approximate Logic Synthesis: An Explainable Machine Learning Approach. ICCAD 2021: 1-9 - [c60]Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu
Lorax: Machine Learning-Based Oracle Reconstruction With Minimal I/O Patterns. ISVLSI 2021: 126-131 - 2020
- [c59]Boyu Zhang, Azadeh Davoodi, Yu Hen Hu:
CHaPR: Efficient Inference of CNNs via Channel Pruning. COINS 2020: 1-6 - [c58]Maedeh Hemmat, Joshua San Miguel
CAP'NN: Class-Aware Personalized Neural Network Inference. DAC 2020: 1-6 - [c57]Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu
Explainable DRC Hotspot Prediction with Random Forest and SHAP Tree Explainer. DATE 2020: 1151-1156 - [i4]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020)
2010 – 2019
- 2019
- [j29]Maedeh Hemmat, Azadeh Davoodi:
Power-efficient ReRAM-aware CNN model generation. Integr. 69: 369-380 (2019) - [j28]Wei Zeng
Analysis of Security of Split Manufacturing Using Machine Learning. IEEE Trans. Very Large Scale Integr. Syst. 27(12): 2767-2780 (2019) - [c56]Maedeh Hemmat, Azadeh Davoodi:
Dynamic Reconfiguration of CNNs for Input-Dependent Approximation. ISQED 2019: 176-182 - [i3]Boyu Zhang, Azadeh Davoodi, Yu Hen Hu:
Efficient Inference of CNNs via Channel Pruning. CoRR abs/1908.03266 (2019) - 2018
- [j27]Boyu Zhang
Exploring Energy and Accuracy Tradeoff in Structure Simplification of Trained Deep Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(4): 836-848 (2018) - [c55]Boyu Zhang, Azadeh Davoodi, Yu Hen Hu:
Exploring energy and accuracy tradeoff in structure simplification of trained deep neural networks. ASP-DAC 2018: 331-336 - [c54]Boyu Zhang, Jonathon Crandall Magaña, Azadeh Davoodi:
Analysis of security of split manufacturing using machine learning. DAC 2018: 141:1-141:6 - [c53]Jackson Melchert, Boyu Zhang, Azadeh Davoodi:
A Comparative Study of Local Net Modeling Using Machine Learning. ACM Great Lakes Symposium on VLSI 2018: 273-278 - [c52]Maedeh Hemmat, Azadeh Davoodi:
Power-Efficient ReRAM-Aware CNN Model Generation. ICCD 2018: 156-162 - [i2]Boyu Zhang, Azadeh Davoodi, Yu Hen Hu:
A Mixture of Expert Approach for Low-Cost Customization of Deep Neural Networks. CoRR abs/1811.00056 (2018) - [i1]Wei Zeng, Azadeh Davoodi, Yu Hen Hu:
Design Rule Violation Hotspot Prediction Based on Neural Network Ensembles. CoRR abs/1811.04151 (2018) - 2017
- [j26]Daohang Shi, Edward Tashjian, Azadeh Davoodi
Dynamic Planning of Local Congestion From Varying-Size Vias for Global Routing Layer Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1301-1312 (2017) - [j25]Jonathon Magaña, Daohang Shi, Jackson Melchert, Azadeh Davoodi
Are Proximity Attacks a Threat to the Security of Split Manufacturing of Integrated Circuits? IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3406-3419 (2017) - [c51]Daniel P. Seemuth, Azadeh Davoodi, Katherine Morrow:
Flexible interconnect in 2.5D ICs to minimize the interposer's metal layers. ASP-DAC 2017: 372-377 - [c50]Daohang Shi, Azadeh Davoodi:
TraPL: Track Planning of Local Congestion for Global Routing. DAC 2017: 19:1-19:6 - [c49]Boyu Zhang, Azadeh Davoodi:
Technology mapping with all spin logic. DATE 2017: 930-933 - [c48]Daohang Shi, Azadeh Davoodi:
Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells. ISPD 2017: 107-112 - 2016
- [j24]Evangeline F. Y. Young, Azadeh Davoodi:
Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology. ACM Trans. Design Autom. Electr. Syst. 21(3): 36:1 (2016) - [c47]Daohang Shi, Edward Tashjian, Azadeh Davoodi:
Dynamic planning of local congestion from varying-size vias for global routing layer assignment. ASP-DAC 2016: 372-377 - [c46]Daohang Shi, Azadeh Davoodi, Jeffrey T. Linderoth:
A procedure for improving the distribution of congestion in global routing. DATE 2016: 249-252 - [c45]Jonathon Magaña, Daohang Shi, Azadeh Davoodi:
Are proximity attacks a threat to the security of split manufacturing of integrated circuits? ICCAD 2016: 90 - 2015
- [j23]Azadeh Davoodi, Jiang Hu, Muhammet Mustafa Ozdal, Cliff C. N. Sze:
Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 501 (2015) - [c44]Edward Tashjian, Azadeh Davoodi:
On using control signals for word-level identification in a gate-level netlist. DAC 2015: 78:1-78:6 - [c43]Amir Yazdanbakhsh
Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors. ACM Great Lakes Symposium on VLSI 2015: 149-154 - [c42]Daniel P. Seemuth, Azadeh Davoodi, Katherine Morrow:
Automatic die placement and flexible I/O assignment in 2.5D IC design. ISQED 2015: 524-527 - [e2]Azadeh Davoodi, Evangeline F. Y. Young:
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29 - April 1, 2015. ACM 2015, ISBN 978-1-4503-3399-3 [contents] - 2014
- [j22]Min Li, Azadeh Davoodi:
A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 1081-1094 (2014) - [c41]Min Li, Azadeh Davoodi:
Multi-mode trace signal selection for post-silicon debug. ASP-DAC 2014: 640-645 - [e1]Cliff C. N. Sze, Azadeh Davoodi:
International Symposium on Physical Design, ISPD'14, Petaluma, CA, USA, March 30 - April 02, 2014. ACM 2014, ISBN 978-1-4503-2592-9 [contents] - 2013
- [j21]Azadeh Davoodi, Min Li, Mohammad Tehranipoor:
A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection. IEEE Des. Test 30(5): 74-82 (2013) - [j20]Hamid Shojaei, Twan Basten
A fast and scalable multidimensional multiple-choice knapsack heuristic. ACM Trans. Design Autom. Electr. Syst. 18(4): 51:1-51:32 (2013) - [j19]Hamid Shojaei, Azadeh Davoodi, Twan Basten
Collaborative Multiobjective Global Routing. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1308-1321 (2013) - [j18]Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth
Power-Driven Global Routing for Multisupply Voltage Domains. VLSI Design 2013: 905493:1-905493:12 (2013) - [c40]Min Li, Azadeh Davoodi:
A hybrid approach for fast and accurate trace signal selection for post-silicon debug. DATE 2013: 485-490 - [c39]Hamid Shojaei, Azadeh Davoodi, Jeffrey T. Linderoth:
Planning for local net congestion in global routing. ISPD 2013: 85-92 - 2012
- [j17]Lin Xie, Azadeh Davoodi:
Post-Silicon Failing-Path Isolation Incorporating the Effects of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 1008-1018 (2012) - [c38]Hamid Shojaei, Azadeh Davoodi, Parmeswaran Ramanathan:
Confidentiality preserving integer programming for global routing. DAC 2012: 709-716 - [c37]Min Li, Azadeh Davoodi, Mohammad Tehranipoor:
A sensor-assisted self-authentication framework for hardware trojan detection. DATE 2012: 1331-1336 - [c36]Min Li, Azadeh Davoodi, Lin Xie:
Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations. DATE 2012: 1591-1596 - 2011
- [j16]Lin Xie, Azadeh Davoodi:
Bound-Based Statistically-Critical Path Extraction Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 59-71 (2011) - [j15]Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth:
GRIP: Global Routing via Integer Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 72-84 (2011) - [c35]Tai-Hsuan Wu, Azadeh Davoodi, Jeff T. Linderoth:
Power-driven global routing for multi-supply voltage domains. DATE 2011: 443-448 - [c34]Hamid Shojaei, Azadeh Davoodi, Jeffrey T. Linderoth:
Congestion analysis for global routing via integer programming. ICCAD 2011: 256-262 - 2010
- [c33]Dongkeun Oh
Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors. ASP-DAC 2010: 593-599 - [c32]Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth:
A parallel integer programming approach to global routing. DAC 2010: 194-199 - [c31]Lin Xie, Azadeh Davoodi, Kewal K. Saluja:
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. DAC 2010: 274-279 - [c30]Lin Xie, Azadeh Davoodi:
Representative path selection for post-silicon timing prediction under variability. DAC 2010: 386-391 - [c29]Hamid Shojaei, Azadeh Davoodi:
Trace signal selection to enhance timing and logic visibility in post-silicon validation. ICCAD 2010: 168-172 - [c28]Hamid Shojaei, Tai-Hsuan Wu, Azadeh Davoodi, Twan Basten
A pareto-algebraic framework for signal power optimization in global routing. ISLPED 2010: 407-412
2000 – 2009
- 2009
- [j14]Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu:
Adjustment-Based Modeling for Timing Analysis Under Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1085-1095 (2009) - [j13]Tai-Hsuan Wu, Azadeh Davoodi:
PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1666-1678 (2009) - [c27]Lin Xie, Azadeh Davoodi:
Bound-based identification of timing-violating paths under variability. ASP-DAC 2009: 278-283 - [c26]Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth:
GRIP: scalable 3D global routing using integer programming. DAC 2009: 320-325 - [c25]Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim:
Statistical static timing analysis considering leakage variability in power gated designs. ISLPED 2009: 57-62 - [c24]Lin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar:
False Path Aware Timing Yield Estimation under Variability. VTS 2009: 161-166 - 2008
- [j12]Lin Xie, Azadeh Davoodi:
Fast and accurate statistical static timing analysis with skewed process parameter variation. IET Circuits Devices Syst. 2(2): 187-200 (2008) - [j11]Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi:
A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing. J. Low Power Electron. 4(2): 191-201 (2008) - [j10]Lin Xie, Azadeh Davoodi:
Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2264-2276 (2008) - [j9]Azadeh Davoodi, Ankur Srivastava
Variability Driven Gate Sizing for Binning Yield Optimization. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 683-692 (2008) - [c23]Tai-Hsuan Wu, Azadeh Davoodi:
PaRS: fast and near-optimal grid-based cell sizing for library-based design. ICCAD 2008: 107-111 - [c22]Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu:
Adjustment-based modeling for statistical static timing analysis with high dimension of variability. ICCAD 2008: 181-184 - [c21]Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi:
SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement. ICCD 2008: 551-556 - [c20]Jungseob Lee, Lin Xie, Azadeh Davoodi:
A Dual-Vt low leakage SRAM array robust to process variations. ISCAS 2008: 580-583 - [c19]Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi:
A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing. ISLPED 2008: 45-50 - [c18]Lin Xie, Azadeh Davoodi:
Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations. ISQED 2008: 156-161 - [c17]Lin Xie, Azadeh Davoodi:
Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation. ISQED 2008: 712-717 - 2007
- [c16]Jennifer L. Wong
Statistical timing analysis using Kernel smoothing. ICCD 2007: 97-102 - [c15]Jungseob Lee, Azadeh Davoodi:
Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations. ISCAS 2007: 3018-3021 - [c14]Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. VLSI Design 2007: 571-576 - 2006
- [j8]Li Wang, Matthew French, Azadeh Davoodi, Deepak Agarwal:
FPGA Dynamic Power Minimization through Placement and Routing Constraints. EURASIP J. Embed. Syst. 2006 (2006) - [j7]Jennifer L. Wong
A statistical methodology for wire-length prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1327-1336 (2006) - [j6]Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
Probabilistic Evaluation of Solutions in Variability-Driven Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 3010-3016 (2006) - [j5]Azadeh Davoodi, Ankur Srivastava
Effective techniques for the generalized low-power binding problem. ACM Trans. Design Autom. Electr. Syst. 11(1): 52-69 (2006) - [c13]Azadeh Davoodi, Ankur Srivastava
Variability driven gate sizing for binning yield optimization. DAC 2006: 959-964 - [c12]Azadeh Davoodi, Ankur Srivastava
Probabilistic evaluation of solutions in variability-driven optimization. ISPD 2006: 17-24 - 2005
- [j4]Azadeh Davoodi, Ankur Srivastava
Voltage scheduling under unpredictabilities: a risk management paradigm. ACM Trans. Design Autom. Electr. Syst. 10(2): 354-368 (2005) - [j3]Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
Simultaneous Vt selection and assignment for leakage optimization. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 762-765 (2005) - [j2]Azadeh Davoodi, Ankur Srivastava
Power-driven simultaneous resource binding and floorplanning: a probabilistic approach. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 934-942 (2005) - [c11]Azadeh Davoodi, Ankur Srivastava:
Simultaneous floorplanning and resource binding: a probabilistic approach. ASP-DAC 2005: 517-522 - [c10]Azadeh Davoodi, Ankur Srivastava
Wake-up protocols for controlling current surges in MTCMOS-based technology. ASP-DAC 2005: 868-871 - [c9]Azadeh Davoodi, Ankur Srivastava
Variability-Driven Buffer Insertion Considering Correlations. ICCD 2005: 425-430 - [c8]Azadeh Davoodi, Ankur Srivastava:
Probabilistic dual-Vth leakage optimization under variability. ISLPED 2005: 143-148 - 2004
- [j1]Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
Empirical models for net-length probability distribution and applications. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1066-1075 (2004) - [c7]Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
High level techniques for power-grid noise immunity. ACM Great Lakes Symposium on VLSI 2004: 13-18 - [c6]Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
Variability inspired implementation selection problem. ICCAD 2004: 423-427 - [c5]Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava:
Efficient statistical timing analysis through error budgeting. ICCAD 2004: 473-477 - [c4]Jennifer L. Wong
Wire-length prediction using statistical techniques. ICCAD 2004: 702-705 - 2003
- [c3]Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava:
A Probabilistic Approach to Buffer Insertion. ICCAD 2003: 560-567 - [c2]Azadeh Davoodi, Ankur Srivastava
Effective graph theoretic techniques for the generalized low power binding problem. ISLPED 2003: 152-157 - [c1]Azadeh Davoodi, Ankur Srivastava:
Voltage scheduling under unpredictabilities: a risk management paradigm. ISLPED 2003: 302-305
Coauthor Index
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