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Aijiao Cui
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2020 – today
- 2024
- [j13]Zhaoxuan Dong
, Aijiao Cui
Non-Invasive Reverse Engineering of One-Hot Finite State Machines Using Scan Dump Data. IEEE Trans. Emerg. Top. Comput. 12(3): 795-809 (2024) - [c41]Xiaolong Cheng, Aijiao Cui, Yier Jin:
A Hardware Security Evaluation Platform on RISC-V SoC. ITC-Asia 2024: 1-6 - 2023
- [c40]Renchao Li
A Lightweight Authentication Scheme with PE-Based Unclonable Label. AsianHOST 2023: 1-6 - [c39]Wei Zhou, Aijiao Cui, Cassi Chen, Gang Qu:
A Low-overhead PUF-based Secure Scan Design. ISQED 2023: 1-6 - 2022
- [j12]Aijiao Cui
SATAM: A SAT Attack Resistant Active Metering Against IC Overbuilding. IEEE Trans. Emerg. Top. Comput. 10(4): 2025-2041 (2022) - [c38]Mengqiang Lu, Aijiao Cui, Yan Shao, Gang Qu:
A Memristor-based Secure Scan Design against the Scan-based Side-Channel Attacks. ACM Great Lakes Symposium on VLSI 2022: 71-76 - [c37]Omid Aramoon, Gang Qu, Aijiao Cui:
Building Hardware Security Primitives Using Scan-based Design-for-Testability. MWSCAS 2022: 1-6 - 2021
- [j11]Aijiao Cui
A New PUF Based Lock and Key Solution for Secure In-Field Testing of Cryptographic Chips. IEEE Trans. Emerg. Top. Comput. 9(2): 1095-1105 (2021) - [j10]Aijiao Cui
Identification of FSM State Registers by Analytics of Scan-Dump Data. IEEE Trans. Inf. Forensics Secur. 16: 5138-5153 (2021) - [c36]Zhenxing Chang, Aijiao Cui, Ziming Wang, Gang Qu:
Novel Memristor-based Nonvolatile D Latch and Flip-flop Designs. ISQED 2021: 244-250 - [c35]Qidong Wang, Aijiao Cui, Gang Qu:
Identification of Counter Registers through Full Scan Chain. ITC-Asia 2021: 1-5 - 2020
- [j9]Aijiao Cui
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4524-4536 (2020) - [c34]Zhichao Xu, Aijiao Cui, Gang Qu:
A New Aging Sensor for the Detection of Recycled ICs. ACM Great Lakes Symposium on VLSI 2020: 223-228 - [c33]Aijiao Cui, Yuxi Wang:
How to Retrieve PUF Response from a Fabricated Chip Securely? ISQED 2020: 21-26 - [c32]Ziming Wang, Aijiao Cui, Gang Qu:
A Low-Cost Fault Injection Attack Resilient FSM Design. SoCC 2020: 19-24 - [c31]Qidong Wang, Aijiao Cui, Gang Qu, Huawei Li:
A New Secure Scan Design with PUF-based Key for Authentication. VTS 2020: 1-6
2010 – 2019
- 2019
- [c30]Chengkang He, Aijiao Cui, Chip-Hong Chang
Identification of State Registers of FSM Through Full Scan by Data Analytics. AsianHOST 2019: 1-6 - [c29]Peiqi Sun, Aijiao Cui:
A New Pay-Per-Use Scheme for the Protection of FPGA IP. ISCAS 2019: 1-5 - [c28]Aijiao Cui, Zhenxing Chang, Ziming Wang, Gang Qu, Huawei Li:
A Memristor-based Scan Hold Flip-Flop. NVMSA 2019: 1-2 - [c27]Aijiao Cui, Yan Yang, Gang Qu, Huawei Li:
A Secure and Low-overhead Active IC Metering Scheme. VTS 2019: 1-6 - 2018
- [c26]Wenxuan Wang, Aijiao Cui, Gang Qu, Huawei Li:
A low-overhead PUF based on parallel scan design. ASP-DAC 2018: 715-720 - [c25]Aijiao Cui, Wei Zhou, Gang Qu, Huawei Li:
A New Scheme to Extract PUF Information by Scan Chain. ATS 2018: 104-108 - [c24]Xi Chen, Omid Aramoon, Gang Qu, Aijiao Cui:
Balancing Testability and Security by Configurable Partial Scan Design. ITC-Asia 2018: 145-150 - [c23]Xi Chen, Zhaojun Lu, Gang Qu, Aijiao Cui:
Partial Scan Design Against Scan-Based Side Channel Attacks. TrustCom/BigDataSE 2018: 1484-1489 - 2017
- [j8]Aijiao Cui, Yanhui Luo, Huawei Li, Gang Qu:
Why current secure scan designs fail and how to fix them? Integr. 56: 105-114 (2017) - [j7]Aijiao Cui
Static and Dynamic Obfuscations of Scan Data Against Scan-Based Side-Channel Attacks. IEEE Trans. Inf. Forensics Secur. 12(2): 363-376 (2017) - [c22]Aijiao Cui, Xuesen Qian, Gang Qu, Huawei Li:
A New Active IC Metering Technique Based on Locking Scan Cells. ATS 2017: 40-45 - [c21]Wei Zhou, Aijiao Cui, Huawei Li, Gang Qu:
How to Secure Scan Design Against Scan-Based Side-Channel Attacks? ATS 2017: 121-126 - [c20]Xi Chen, Gang Qu, Aijiao Cui:
Practical IP watermarking and fingerprinting methods for ASIC designs. ISCAS 2017: 1-4 - [c19]Xiaonan Huang, Aijiao Cui, Chip-Hong Chang
A new watermarking scheme on scan chain ordering for hard IP protection. ISCAS 2017: 1-4 - [c18]Xi Chen, Gang Qu, Aijiao Cui, Carson Dunbar:
Scan chain based IP fingerprint and identification. ISQED 2017: 264-270 - 2016
- [c17]Jiadong Wang, Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li:
An ultra-low overhead LUT-based PUF for FPGA. AsianHOST 2016: 1-6 - [c16]Yanhui Luo, Aijiao Cui, Gang Qu, Huawei Li:
A new countermeasure against scan-based side-channel attacks. ISCAS 2016: 1722-1725 - [c15]Lucheng He, Aijiao Cui, Mengyang Li, André Ivanov:
An improved test power optimization method by insertion of linear functions. ISCAS 2016: 2631-2634 - [p1]Gang Qu, Carson Dunbar, Xi Chen, Aijiao Cui:
Digital Fingerprint: A Practical Hardware Security Primitive. Digital Fingerprinting 2016: 89-114 - 2015
- [j6]Linfeng Chen, Aijiao Cui, Chip-Hong Chang
Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction. IEEE Trans. Computers 64(12): 3417-3429 (2015) - [j5]Aijiao Cui, Gang Qu, Yan Zhang:
Ultra-Low Overhead Dynamic Watermarking on Scan Design for Hard IP Protection. IEEE Trans. Inf. Forensics Secur. 10(11): 2298-2313 (2015) - [c14]Mingze Gao, Khai Lai, Jiliang Zhang, Gang Qu, Aijiao Cui, Qiang Zhou:
Reliable and Anti-cloning PUFs Based on Configurable Ring Oscillators. CAD/Graphics 2015: 194-201 - [c13]Aijiao Cui, Tingting Yu, Gang Qu, Mengyang Li:
An improved scan design for minimization of test power under routing constraint. ISCAS 2015: 629-632 - [c12]Tingting Yu, Aijiao Cui, Mengyang Li, André Ivanov:
A new decompressor with ordered parallel scan design for reduction of test data and test time. ISCAS 2015: 641-644 - 2014
- [j4]Ruiyi Sun, Yan Zhang, Aijiao Cui:
A refined affine approximation method of multiplication for range analysis in word-length optimization. EURASIP J. Adv. Signal Process. 2014: 36 (2014) - [c11]Aijiao Cui, Wei Liang, Gang Qu:
A low-overhead dynamic watermarking scheme on scan design for easy authentication. ISCAS 2014: 778-781 - [c10]Mengyang Li, Aijiao Cui, Tingting Yu:
An improved scan cell ordering method using the scan cells with complementary outputs. ISIC 2014: 103-106 - 2013
- [c9]Yongxia Liu, Aijiao Cui:
An Efficient Zero-Aliasing Space Compactor Based on Elementary Gates Combined with XOR Gates. CAD/Graphics 2013: 95-100 - [c8]Linfeng Chen, Aijiao Cui:
A power-efficient scan tree design by exploring the Q'-D connection. ISCAS 2013: 1018-1021 - 2012
- [c7]Aijiao Cui, Chip-Hong Chang
A post-processing scan-chain watermarking scheme for VLSI intellectual property protection. APCCAS 2012: 412-415 - 2011
- [j3]Aijiao Cui, Chip-Hong Chang
A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 678-690 (2011) - [c6]Aijiao Cui, Chip-Hong Chang
A hybrid watermarking scheme for sequential functions. ISCAS 2011: 2333-2336 - 2010
- [j2]Chip-Hong Chang
Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1618-1630 (2010)
2000 – 2009
- 2009
- [c5]Aijiao Cui, Chip-Hong Chang
An Improved Publicly Detectable Watermarking Scheme based on Scan Chain Ordering. ISCAS 2009: 29-32 - 2008
- [j1]Aijiao Cui, Chip-Hong Chang
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1565-1570 (2008) - [c4]Aijiao Cui, Chip-Hong Chang
Intellectual property authentication by watermarking scan chain in design-for-testability flow. ISCAS 2008: 2645-2648 - 2007
- [c3]Aijiao Cui, Chip-Hong Chang:
Watermarking for IP Protection through Template Substitution at Logic Synthesis Level. ISCAS 2007: 3687-3690 - 2006
- [c2]Aijiao Cui, Chip-Hong Chang
Kernel Extraction for Watermarking Combinational Logic Networks. APCCAS 2006: 1023-1026 - [c1]Aijiao Cui, Chip-Hong Chang:
Stego-signature at logic synthesis level for digital design IP protection. ISCAS 2006
Coauthor Index
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last updated on 2024-10-15 20:42 CEST by the dblp team
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