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Ja-Yol Lee

Jayol Lee

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2020 – today

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2022
[j3]
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Minuk Heo, Sunghyun Bae, Ja-Yol Lee, Cheonsu Kim, Minjae Lee:
A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications. IEEE Access 10: 62471-62483 (2022)
2021
[c5]
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Jayol Lee, Youngseok Baek, Iksoo Eo, Bontae Koo:
A Ka-Band FMCW PLL Synthesizer with 8.5-GHz Bandwidth for High-Precision High-Resolution Sub-mmWave Radar Sensing. ISCAS 2021: 1-5
2020
[j2]
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Jayol Lee, Cheon-Soo Kim, Jang Hong Choi, Ki Su Kim, Bon Tae Koo:
Untrimmed BGR of 1.1% $3\sigma$ Based on Dynamic-Biased Op Amp With Reduced ${V} _{\rm off}$. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1829-1833 (2020)

2010 – 2019

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2015
[c4]
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Wooyeol Choi, Zeshan Ahmad, Amit Jha, Ja-Yol Lee, Insoo Kim, Kenneth K. O:
410-GHz CMOS imager using a 4^th sub-harmonic mixer with effective NEP of 0.3 fW/Hz^0.5 at 1-kHz noise bandwidth. VLSIC 2015: 302-
2014
[c3]
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  - conf/mwscas/LeePYK14
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Ja-Yol Lee, Mi-Jeong Park, Hyun-Kyu Yu, Cheon-Soo Kim:
A 230ns settling time type-I PLL with 0.96mW TDC power and simple TV calculation algorithm. MWSCAS 2014: 370-373
2012
[j1]
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Ja-Yol Lee, Mi-Jeong Park, Byung-Hun Min, Seongdo Kim, Mun-Yang Park, Hyun-Kyu Yu:
A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1706-1719 (2012)
2011
[c2]
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Ja-Yol Lee, Mi-Jeong Park, Byonghoon Mhin, Seongdo Kim, Moon-Yang Park, Hyunku Yu:
A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation. CICC 2011: 1-4

2000 – 2009

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2006
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Ja-Yol Lee, Kwi-Dong Kim, Jong-Kee Kwon, Seung-Chul Lee, Jongdae Kim, Sang-Heung Lee:
A 3.8-5.5-GHz Multi-Band CMOS Frequency Synthesizer for WPAN/WLAN Applications. CICC 2006: 377-380

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