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Francesca Lo Cicero
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2020 – today
- 2024
- [j7]María Engracia Gómez
, Julio Sahuquillo, Andrea Biagioni, Nikos Chrysos, Damien Berton, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Francesco Simula, Matteo Turisini, Piero Vicini, Roberto Ammendola, Carlotta Chiarini, Chiara De Luca, Fabrizio Capuani, Adrián Castelló, Jose Duro, Eugenio Stabile, Enrique S. Quintana-Ortí, Pascale Bernier-Bruna, Claire Chen, Pierre-Axel Lagadec, Gregoire Pichon, Etienne Walter, Manolis Katevenis, Sokratis Bartzis, Orestis Mousouros, Pantelis Xirouchakis, Vangelis Mageiropoulos, Michalis Gianioudis, Harisis Loukas, Aggelos Ioannou, Nikos Kallimanis, Miguel Sánchez de la Rosa, Gabriel Gomez-Lopez, Francisco Alfaro-Cortés, Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José L. Sánchez, Gaetan De Gassowski, Matthieu Hautreaux, Stephane Mathieu, Gilles Moreau, Marc Pérache, Hugo Taboada, Torsten Hoefler, Timo Schneider, Matteo Barnaba, Giuseppe Piero Brandino, Francesco De Giorgi, Matteo Poggi, Iakovos Mavroidis, Yannis Papaefstathiou, Nikolaos Tampouratzis, Benjamin Kalisch, Ulrich Krackhardt, Mondrian Nuessle, Wolfgang Frings, Dominik Gottwald, Felime Guimaraes, Max Holicki, Volker Marx, Yannik Müller, Carsten Clauss, Hugo Falter, Xu Huang, Jennifer Lopez Barillao, Thomas Moschny, Simon Pickartz:
RED-SEA Project: Towards a new-generation European interconnect. Microprocess. Microsystems 110: 105102 (2024) - [c15]Roberto Ammendola, Andrea Biagioni, Carlotta Chiarini, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Luca Pontisso, Cristian Rossi, Francesco Simula, Piero Vicini:
APEnetX: A Custom NIC for Cluster Interconnects. DSD 2024: 90-97 - [c14]Antonio Filgueras, Giovanni Agosta, Marco Aldinucci, Carlos Álvarez, Pasqua D'Ambra, Massimo Bernaschi, Andrea Biagioni, Daniele Cattaneo, Alessandro Celestini, Massimo Celino, Carlotta Chiarini, Francesca Lo Cicero, Paolo Cretaro, William Fornaciari, Ottorino Frezza, Andrea Galimberti, Francesco Giacomini, Juan Miguel De Haro Ruiz, Francesco Iannone, Daniel Jaschke, Daniel Jiménez-González, Michal Kulczewski, Alberto Leva, Alessandro Lonardo, Michele Martinelli, Xavier Martorell, Simone Montangero, Lucas Morais, Ariel Oleksiak, Paolo Palazzari, Luca Pontisso, Federico Reghenzani, Cristian Rossi, Sergio Saponara, Carlo Saverio Lodi, Francesco Simula, Federico Terraneo, Piero Vicini, Miquel Vidal, Davide Zoni, Giuseppe Zummo:
The TEXTAROSSA Project: Cool all the Way Down to the Hardware. DSD 2024: 526-533 - 2023
- [i20]Roberto Ammendola, Andrea Biagioni, Carlotta Chiarini, Andrea Ciardiello, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Cristian Rossi, Francesco Simula, Matteo Turisini, Piero Vicini:
APEIRON: composing smart TDAQ systems for high energy physics experiments. CoRR abs/2307.01009 (2023) - 2022
- [j6]Giovanni Agosta, Marco Aldinucci, Carlos Álvarez
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach. Microprocess. Microsystems 95: 104679 (2022) - [c13]Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci
RED-SEA: Network Solution for Exascale Architectures. DSD 2022: 712-719 - [i19]Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Alessandro Lonardo, Francesca Lo Cicero, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini:
Architectural improvements and technological enhancements for the APEnet+ interconnect system. CoRR abs/2201.01088 (2022) - 2021
- [c12]Giovanni Agosta, Daniele Cattaneo, William Fornaciari
TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale. DSD 2021: 286-294
2010 – 2019
- 2019
- [c11]Francesco Simula
Real-Time Cortical Simulations: Energy and Interconnect Scaling on Distributed Systems. PDP 2019: 283-290 - 2018
- [j5]Manolis Katevenis, Roberto Ammendola
Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development. Microprocess. Microsystems 61: 58-71 (2018) - [c10]Elena Pastorelli
Gaussian and Exponential Lateral Connectivity on Distributed Spiking Neural Network Simulation. PDP 2018: 658-665 - [i18]Elena Pastorelli
Gaussian and exponential lateral connectivity on distributed spiking neural network simulation. CoRR abs/1803.08833 (2018) - [i17]Roberto Ammendola, Andrea Biagioni, Fabrizio Capuani, Paolo Cretaro, Giulia De Bonis, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Luca Pontisso, Francesco Simula, Piero Vicini:
The Brain on Low Power Architectures - Efficient Simulation of Cortical Slow Waves and Asynchronous States. CoRR abs/1804.03441 (2018) - [i16]Roberto Ammendola, Andrea Biagioni, Fabrizio Capuani, Paolo Cretaro, Giulia De Bonis, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Luca Pontisso, Francesco Simula, Piero Vicini:
Large Scale Low Power Computing System - Status of Network Design in ExaNeSt and EuroExa Projects. CoRR abs/1804.03893 (2018) - [i15]Francesco Simula, Elena Pastorelli, Pier Stanislao Paolucci
Real-time cortical simulations: energy and interconnect scaling on distributed systems. CoRR abs/1812.04974 (2018) - 2017
- [j4]Daniele Cesini
Power-Efficient Computing: Experiences from the COSA Project. Sci. Program. 2017: 7206595:1-7206595:14 (2017) - [c9]Roberto Ammendola, Andrea Biagioni
The Next Generation of Exascale-Class Systems: The ExaNeSt Project. DSD 2017: 510-515 - [c8]Roberto Ammendola
Large Scale Low Power Computing System - Status of Network Design in ExaNeSt and EuroExa Projects. PARCO 2017: 750-759 - [c7]Roberto Ammendola
The Brain on Low Power Architectures - Efficient Simulation of Cortical Slow Waves and Asynchronous States. PARCO 2017: 760-769 - [c6]Daniele Cesini, Elena Corni, Antonio Falabella, Andrea Ferraro, Luca Lama
The INFN COSA Project: Low-Power Computing and Storage. PARCO 2017: 770-779 - 2016
- [j3]Pier Stanislao Paolucci
Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms. J. Syst. Archit. 69: 29-53 (2016) - [c5]Manolis Katevenis, Nikolaos Chrysos, Manolis Marazakis, Iakovos Mavroidis, Fabien Chaix, Nikolaos D. Kallimanis
The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems. DSD 2016: 60-67 - 2015
- [j2]Roberto Ammendola
A hierarchical watchdog mechanism for systemic fault awareness on distributed systems. Future Gener. Comput. Syst. 53: 90-99 (2015) - [j1]Roberto Ammendola
ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces. Future Gener. Comput. Syst. 53: 109-118 (2015) - [i14]Pier Stanislao Paolucci
Power, Energy and Speed of Embedded and Server Multi-Cores applied to Distributed Simulation of Spiking Neural Networks: ARM in NVIDIA Tegra vs Intel Xeon quad-cores. CoRR abs/1505.03015 (2015) - [i13]Elena Pastorelli, Pier Stanislao Paolucci
Scaling to 1024 software processes and hardware cores of the distributed simulation of a spiking neural network including up to 20G synapses. CoRR abs/1511.09325 (2015) - [i12]Elena Pastorelli, Pier Stanislao Paolucci
Impact of exponential long range and Gaussian short range lateral connectivity on the distributed simulation of neural networks including up to 30 billion synapses. CoRR abs/1512.05264 (2015) - 2014
- [c4]Roberto Ammendola
LO-FA-MO: Fault Detection and Systemic Awareness for the QUonG Computing System. SRDS 2014: 265-270 - [i11]Alessandro Lonardo, F. Ameli, Roberto Ammendola, Andrea Biagioni
NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features. CoRR abs/1406.3568 (2014) - [i10]Pier Stanislao Paolucci
EURETILE D7.3 - Dynamic DAL benchmark coding, measurements on MPI version of DPSNN-STDP (distributed plastic spiking neural net) and improvements to other DAL codes. CoRR abs/1408.4587 (2014) - 2013
- [c3]Roberto Ammendola
Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities. FPT 2013: 58-65 - [c2]Roberto Ammendola
GPU Peer-to-Peer Techniques Applied to a Cluster Interconnect. IPDPS Workshops 2013: 806-815 - [c1]Roberto Ammendola
Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface. ReConFig 2013: 1-6 - [i9]Roberto Ammendola, Andrea Biagioni
'Mutual Watch-dog Networking': Distributed Awareness of Faults and Critical Events in Petascale/Exascale systems. CoRR abs/1307.0433 (2013) - [i8]Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Werner Geurts, Gert Goossens, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini
A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report. CoRR abs/1307.1270 (2013) - [i7]Roberto Ammendola, Massimo Bernaschi, Andrea Biagioni, Mauro Bisson, Massimiliano Fatica, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Enrico Mastrostefano, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini:
GPU peer-to-peer techniques applied to a cluster interconnect. CoRR abs/1307.8276 (2013) - [i6]Pier Stanislao Paolucci, Roberto Ammendola, Andrea Biagioni
Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster. CoRR abs/1310.8478 (2013) - [i5]Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Pier Stanislao Paolucci, Alessandro Lonardo, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini:
Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems. CoRR abs/1311.1741 (2013) - [i4]Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, G. Lamanna, Alessandro Lonardo, Francesca Lo Cicero, Pier Stanislao Paolucci, F. Pantaleo, Davide Rossetti, Francesco Simula, M. Sozzi, Laura Tosoratto, Piero Vicini:
NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs. CoRR abs/1311.4007 (2013) - 2012
- [i3]Andrea Biagioni
The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture. CoRR abs/1203.1536 (2012) - 2011
- [i2]Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Andrea Salamon, Gaetano Salina, Francesco Simula, Laura Tosoratto, Piero Vicini:
APEnet+: high bandwidth 3D torus direct network for petaflops scale commodity clusters. CoRR abs/1102.3796 (2011) - 2010
- [i1]Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci
APEnet+: a 3D toroidal network enabling Petaflops scale Lattice QCD simulations on commodity clusters. CoRR abs/1012.0253 (2010)
Coauthor Index
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last updated on 2024-12-10 20:50 CET by the dblp team
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