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Yi Kang
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2020 – today
- 2024
- [j29]Haitao Du
, Yuhan Qin
FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration. ACM Trans. Archit. Code Optim. 21(2): 34 (2024) - [j28]Junkaixuan Li
GraphSER: Distance-Aware Stream-Based Edge Repartition for Many-Core Systems. ACM Trans. Archit. Code Optim. 21(3): 48:1-48:25 (2024) - [j27]Wenhao Sun
Bit-Balance: Model-Hardware Codesign for Accelerating NNs by Exploiting Bit-Level Sparsity. IEEE Trans. Computers 73(1): 152-163 (2024) - [j26]Junpeng Wang
NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators With 3-D Stacked-DRAM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1456-1469 (2024) - [j25]Qi Xu
Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3754-3763 (2024) - [j24]Yongtian Bi
AD2VNCS: Adversarial Defense and Device Variation-tolerance in Memristive Crossbar-based Neuromorphic Computing Systems. ACM Trans. Design Autom. Electr. Syst. 29(1): 8:1-8:19 (2024) - [j23]Bo Yang
Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay. ACM Trans. Design Autom. Electr. Syst. 29(3): 56:1-56:17 (2024) - [j22]Xiang Zhao, Song Chen, Yi Kang:
Load Balanced PIM-Based Graph Processing. ACM Trans. Design Autom. Electr. Syst. 29(4): 1-22 (2024) - [c44]Ke Hu, Tongbo Cao, Yuan Li, Song Chen, Yi Kang:
DALDet: Depth-Aware Learning Based Object Detection for Autonomous Driving. AAAI 2024: 2229-2237 - [c43]Yazhuo Guo, Yuhan Qin, Song Chen, Yi Kang:
SPVT: Spiked Pyramid Vision Transformer. AICAS 2024: 110-113 - [c42]Yuhan Qin, Yulong Meng, Haitao Du, Yazhuo Guo, Yi Kang:
MSCA: Model-Driven Search for Optimal Configuration for SpMM Accelerators. AICAS 2024: 592-596 - [c41]Yuxuan Yang, Zihao Xuan, Yi Kang:
TQ-TTFS: High-Accuracy and Energy-Efficient Spiking Neural Networks Using Temporal Quantization Time-to-First-Spike Neuron. ASPDAC 2024: 836-841 - [c40]Bing Li, Wendi Sun, Xiaobing Ni, Kaixuan He, Qi Xu, Song Chen, Yi Kang:
Parallel Multi-Objective Bayesian Optimization Framework for CGRA Microarchitecture. DATE 2024: 1-6 - [c39]Bo Yang, Qi Xu, Hao Geng, Song Chen, Yi Kang:
Miracle: Multi-Action Reinforcement Learning-Based Chip Floorplanning Reasoner. DATE 2024: 1-6 - [c38]Wendi Sun
Communication Minimized Model-Architecture Co-design for Efficient Convolution Acceleration. ACM Great Lakes Symposium on VLSI 2024: 144-150 - [c37]Jie Tang, Shuai Wang, Song Chen, Yi Kang:
DP-FFN: Block-Based Dynamic Pooling for Accelerating Feed-Forward Layers in Transformers. ISCAS 2024: 1-5 - [c36]Shuai Wang
AFT-CIM: An Energy Efficient ADC-Free Transpose Computing-in-Memory Macro for MAC Operations. ISCAS 2024: 1-5 - [i10]Mengke Ge, Junpeng Wang, Binhan Chen, Yingjian Zhong, Haitao Du, Song Chen, Yi Kang:
Allspark: Workload Orchestration for Visual Transformers on Processing In-Memory Systems. CoRR abs/2403.15069 (2024) - 2023
- [j21]Yi Kang
Self-Supervised Node Classification with Strategy and Actively Selected Labeled Set. Entropy 25(1): 30 (2023) - [j20]Shuai Wang
Gradient distribution-aware INT8 training for neural networks. Neurocomputing 541: 126269 (2023) - [j19]Yi Kang
Ghost key distribution under mutual authentication mechanism. Inf. Sci. 640: 119025 (2023) - [j18]Yi Kang, Leihong Zhang, Hualong Ye, Baolin Liu, Shengli Pu
Visual cryptography based on ghost imaging and Hadamard transform. Quantum Inf. Process. 22(2): 116 (2023) - [j17]Qi Xu
Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems. IEEE Trans Autom. Sci. Eng. 20(1): 74-87 (2023) - [j16]Zihao Xuan
A Brain-Inspired ADC-Free SRAM-Based In-Memory Computing Macro With High-Precision MAC for AI Application. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1276-1280 (2023) - [j15]Yongtian Bi, Qi Xu
Resist: Robust Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 2221-2225 (2023) - [j14]Xiaobing Ni, Mengke Ge
BusMap: Application Mapping With Bus Routing for Coarse-Grained Reconfigurable Array. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3054-3058 (2023) - [j13]Bo Ding
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. ACM Trans. Design Autom. Electr. Syst. 28(1): 7:1-7:21 (2023) - [j12]Junpeng Wang
DDAM: Data Distribution-Aware Mapping of CNNs on Processing-In-Memory Systems. ACM Trans. Design Autom. Electr. Syst. 28(3): 36:1-36:30 (2023) - [j11]Bo Ding
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources. ACM Trans. Design Autom. Electr. Syst. 28(6): 103:1-103:26 (2023) - [j10]Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Song Chen
Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 470-483 (2023) - [c35]Chunhui Wu, Wenbing Fang, Yi Kang:
HNSG - A SNN Training Method Ultilizing Hidden Network. AICAS 2023: 1-5 - [c34]Yue Zhang, Shuai Wang, Yi Kang:
MF-DSNN:An Energy-efficient High-performance Multiplication-free Deep Spiking Neural Network Accelerator. AICAS 2023: 1-4 - [c33]Haohan Zhang, Song Cheng, Yi Kang:
FlsGraph: A Parallel Architecture for Large-scale Graph Processing. ASICON 2023: 1-4 - [c32]Yuchao Zhang, Zihao Xuan, Yi Kang:
A 28nm 15.09nJ/inference Neuromorphic Processor with SRAM-Based Charge Domain in-Memory-Computing. ASICON 2023: 1-4 - [c31]Wenbing Fang, Zihao Xuan, Song Chen, Yi Kang:
An 1.38nJ/Inference Clock-Free Mixed-Signal Neuromorphic Architecture Using ReL-PSP Function and Computing-in-Memory. BioCAS 2023: 1-5 - [c30]Bin Zhang
GGPA: A General Graph Processing Architecture with Flexible Execution Paradigm. CF 2023: 33-41 - [c29]Zetao Guo, Junpeng Wang, Song Chen, Yi Kang:
A Lightweight Stereo Matching Neural Network Based on Depthwise Separable Convolution. ICTA 2023: 122-123 - [c28]Junyan Sun, Xuefei Bai
An FPGA-Based Efficient NTT Accelerator for Post-Quantum Cryptography CRYSTALS-Kyber. ICTA 2023: 142-143 - [c27]Song Wang, Bing Yu, Wenwu Xiao, Fujun Bai, Xiaodong Long, Liang Bai, Xuerong Jia, Fengguo Zuo, Jie Tan, Yixin Guo
A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV. VLSI Technology and Circuits 2023: 1-2 - [i9]Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen, Yi Kang:
Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity. CoRR abs/2302.00201 (2023) - [i8]Junpeng Wang, Mengke Ge, Bo Ding, Qi Xu, Song Chen, Yi Kang:
NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM. CoRR abs/2305.19041 (2023) - [i7]Xiaobing Ni, Jiaheng Ruan, Mengke Ge, Wendi Sun, Song Chen, Yi Kang:
BandMap: Application Mapping with Bandwidth Allocation forCoarse-Grained Reconfigurable Array. CoRR abs/2310.06613 (2023) - [i6]Zihao Xuan, Song Chen, Yi Kang:
AiDAC: A Low-Cost In-Memory Computing Architecture with All-Analog Multi-Bit Compute and Interconnect. CoRR abs/2312.11836 (2023) - [i5]Wenhao Sun, Wendi Sun, Song Chen, Yi Kang:
IOPS: An Unified SpMM Accelerator Based on Inner-Outer-Hybrid Product. CoRR abs/2312.12766 (2023) - [i4]Qi Xu, Lijie Wang, Jing Wang, Song Chen, Lin Cheng, Yi Kang:
Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits. CoRR abs/2312.14405 (2023) - 2022
- [j9]Ke Hu, Wenhao Sun, Zhongbo Nie, Ran Cheng, Song Chen
Real-time infrared small target detection network and accelerator design. Integr. 87: 241-252 (2022) - [j8]Qi Xu
Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1196-1208 (2022) - [j7]Qi Xu
Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3182-3187 (2022) - [j6]Qi Xu
GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3492-3502 (2022) - [j5]Mengke Ge
Generating Brain-Network-Inspired Topologies for Large-Scale NoCs on Monolithic 3D ICs. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1552-1556 (2022) - [j4]Mengke Ge, Xiaobing Ni, Qi Xu, Song Chen
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips. ACM Trans. Design Autom. Electr. Syst. 27(1): 9:1-9:30 (2022) - [j3]Zihao Xuan
High-Efficiency Data Conversion Interface for Reconfigurable Function-in-Memory Computing. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1193-1206 (2022) - [c26]Qiaojun Wu, Yuan Li, Song Chen, Yi Kang:
DRGS: Low-Precision Full Quantization of Deep Neural Network with Dynamic Rounding and Gradient Scaling for Object Detection. DMBD (1) 2022: 137-151 - [c25]Yidi Chang, Zhi Liu, Haifeng Yao
Demonstration of 8Gb/s 4-PAM Signal All-optical Wavelength Conversion Transmission under Simulated Atmospheric Laser Communication Network. ICAIT 2022: 85-89 - [c24]Mingxue Shi, Zhi Liu, Yi Kang, Haifeng Yao
Adaptive Turbulence Channel Equalization Based on Neural Network. ICAIT 2022: 142-145 - [c23]Yifan Song, Shunpeng Zhao, Song Chen, Yi Kang:
SAUST: A Scheme for Acceleration of Unstructured Sparse Transformer. ICTA 2022: 56-57 - [c22]Bin Zhang, Haitao Du
PCFBCD: An Innovative Approach to Accelerating Collaborative Filtering. ISCAS 2022: 2675-2679 - [c21]Zihao Xuan
HPSW-CIM: A Novel ReRAM-Based Computing-in-Memory Architecture with Constant-Term Circuit for Full Parallel Hybrid-Precision-Signed-Weight MAC Operation. ISCAS 2022: 3274-3278 - [c20]Yuan Li, Qiaojun Wu, Song Chen, Yi Kang:
Multi-scale Lightweight Neural Network for Real-Time Object Detection. PRICAI (3) 2022: 199-211 - [i3]Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Junpeng Wang, Yi Kang, Song Chen:
Sense: Model Hardware Co-design for Accelerating Sparse Neural Networks. CoRR abs/2202.00389 (2022) - [i2]Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang:
Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs. CoRR abs/2212.05397 (2022) - 2021
- [j2]Chunyu Liu
Rapidly Decoding Image Categories From MEG Data Using a Multivariate Short-Time FC Pattern Analysis Approach. IEEE J. Biomed. Health Informatics 25(4): 1139-1150 (2021) - [c19]Mingjian Sun, Yuan Li, Song Chen, Yi Kang:
A Low Power Branch Prediction for Deep Learning on RISC-V Processor. ASAP 2021: 203-206 - [c18]Chang Liu, Zihao Xuan
A 40-nm 202.3nJ/Classification Neuromorphic Architecture Employing In-SRAM Charge-Domain Compute. ASICON 2021: 1-4 - [c17]Xiping Jiang, Fengguo Zuo, Song Wang, Xiaofeng Zhou, Bing Yu, Yubing Wang, Qi Liu, Ming Liu, Yi Kang, Qiwei Ren:
A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration. A-SSCC 2021: 1-3 - [c16]Jing Wang, Ping Chen, Cheng Zhang, Yi Kang:
Corona Virus Disease 2019 Respiratory Cycle Detection Based on Convolutional Neural Network. BioCAS 2021: 1-4 - [c15]Lei Ding, Haitao Du
A Low-latency NoC Router Priority Scheme for BFS algorithm. ICTA 2021: 271-272 - [c14]Qiqiao Wu, Wenhao Sun, Junpeng Wang, Xuefei Bai, Feng Zhang, Song Chen, Yi Kang:
A Non-volatile Computing-in-Memory ReRAM Macro using Two-bit Current-Mode Sensing Amplifier. NVMSA 2021: 1-6 - [i1]Mengke Ge, Xiaobing Ni, Qi Xu, Song Chen, Jinglei Huang, Yi Kang, Feng Wu:
Synthesizing Brain-Network-Inspired Interconnections for Large-Scale Network-on-Chips. CoRR abs/2108.01298 (2021) - 2020
- [c13]Mengke Ge, Qi Xu, Huajie Ruan, Xiaobing Ni, Song Chen, Yi Kang:
Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems. ACM Great Lakes Symposium on VLSI 2020: 303-308
2010 – 2019
- 2019
- [c12]Baicheng Liu, Song Chen, Yi Kang, Feng Wu:
An Energy-Efficient Systolic Pipeline Architecture for Binary Convolutional Neural Network. ASICON 2019: 1-4 - [c11]Tianzhi Xue, Baicheng Liu, Wenhao Sun, Song Chen, Yi Kang, Feng Wu:
Customizing CMOS/ReRAM Hybrid Hardware Architecture for Spiking CNN. ASICON 2019: 1-4 - 2018
- [c10]Yi Kang:
AI Drives Domain Specific Processors. A-SSCC 2018: 13-16 - [c9]Yuzheng Tao, Gang Wu, Yi Kang:
Stargate: a data source connector based on spark SQL. ICMLSC 2018: 98-103 - 2014
- [c8]Linlin Wang, Shiji Xiahou, Yi Kang:
The Interactive Design and Performance Study of Instrument Panels Based on the Single-Handed Keyboard Mouse. CSE 2014: 1616-1620 - 2012
- [c7]Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Pratap Pattnaik, Josep Torrellas:
FlexRAM: Toward an advanced Intelligent Memory system. ICCD 2012: 5-14
2000 – 2009
- 2009
- [j1]Yaqiang Ding, Fuhuei Lin, Jiang Lin, Yi Wang, Yi Kang:
A novel system multiplexing and program element identification scheme. IEEE Trans. Consumer Electron. 55(2): 749-753 (2009) - 2008
- [c6]Qingsheng Yuan, Yiqiang Chen, Yi Kang:
A fast region-based inter mode selection algorithm. ICME 2008: 829-832 - 2007
- [c5]Yaqiang Ding, Jiang Lin, Yi Wang, Fuhuei Lin, Yi Kang:
A Scheme for System Multiplexing and Program Component Identification. ICME 2007: 583-586 - [c4]Wen Ji, Yiqiang Chen, Min Chen, Yi Kang:
Unequal error protection based on objective video evaluation model. MobiMedia 2007: 5
1990 – 1999
- 1999
- [b1]Yi Kang:
An Intelligent Memory for Data -Parallel Applications. University of Illinois Urbana-Champaign, USA, 1999 - [c3]Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik:
FlexRAM: Toward an Advanced Intelligent Memory System. ICCD 1999: 192-201 - 1998
- [c2]Yi Kang, Josep Torrellas, Thomas S. Huang:
Use IRAM for Rasterization. ICIP (3) 1998: 1010-1013 - [c1]Yi Kang, Josep Torrellas, Thomas S. Huang:
An IRAM architecture for image analysis and pattern recognition. ICPR 1998: 1561-1564
Coauthor Index
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last updated on 2024-12-04 20:12 CET by the dblp team
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