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Jian-Hsing Lee

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2020 – today

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2024
[c23]
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  - conf/icce-tw/ChenCWCCCCL24
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Chun-Chih Chen, Shih-Chieh Chien, Chien-Wei Wang, Yu-Sheng Chiu, Jung-Tsun Chuang, Li-Fan Chen, Chieh-Yao Chuang, Jian-Hsing Lee:
The Influence of the Block Design on the ID-VD Curves of Power Transistor for E-SOA Characterization. ICCE-Taiwan 2024: 779-780
[c22]
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Yeh-Jen Huang, Li-Yang Hong, Yeh-Ning Jou, Jian-Hsing Lee:
Negative Triggering Current Induced the Latch-up in the Circuit without the ESD device to Power. ICCE-Taiwan 2024: 781-782
2023
[c21]
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Shao-Chang Huang, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Chien-Wei Wang, Gong-Kai Lin, Lin-Fan Chen, Chun-Chih Chen, Kuan-I Ho, Che-Hua Chang, Hsiao-Ying Yang, Chung-Ren Lao, Jian-Hsing Lee, Ke-Horng Chen:
Optimizing Device Metal Routing Layouts by the Simulation Tool. ICCE-Taiwan 2023: 219-220
[c20]
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Shao-Chang Huang, Kai-Chieh Hsu, Chih-Hsuan Lin, Chien-Wei Wang, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Gong-Kai Lin, Lin-Fan Chen, Chun-Chih Chen, Yeh-Ning Jou, Jian-Hsing Lee, Ke-Horng Chen:
Bipolar Transistors' Holding Phenomena. ICCE-Taiwan 2023: 221-222
[c19]
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Shao-Chang Huang, Chien-Wei Wang, Chih-Hsuan Lin, Kai-Chieh Hsu, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Gong-Kai Lin, Lin-Fan Chen, Chun-Chih Chen, Yeh-Ning Jou, Jian-Hsing Lee, Ke-Horng Chen:
Transmission Line Pulse Width Impacting on Device Performances. ICCE-Taiwan 2023: 227-228
[c18]
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Jian-Hsing Lee, Gong-Kai Lin, Chun-Chih Chen, Li-Fan Chen, Chien-Wei Wang, Shao-Chang Huang, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Ke-Horng Chen:
A Concise Electrothermal Model to Characterize the Thermal Safe-Operating Area of Power Transistor. IRPS 2023: 1-6
2022
[c17]
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Shao-Chang Huang, Jian-Hsing Lee, Chun-Chih Chen, Ching-Ho Li, Chih-Cherng Liao, Kai-Chieh Hsu, Gong-Kai Lin, Li-Fan Chen, Chien-Wei Wang, Chih-Hsuan Lin, Yeh-Ning Jou, Ke-Horng Chen:
Gate Voltages Impacting on Latch-up Measurements. ICCE-TW 2022: 75-76
[c16]
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Shao-Chang Huang, Jian-Hsing Lee, Ching-Ho Li, Sue-Yi Chen, Chih-Hsuan Lin, Chun-Chih Chen, Li-Fan Chen, Gong-Kai Lin, Chien-Wei Wang, Kai-Chieh Hsu, Szu-Chi Chen, Shang-Chuan Pai, Fu-Wei Pai, Yin-Wei Peng, Chih-Cherng Liao, Ke-Horng Chen:
EOS Endurance Power Circuits without Depletion Mode Devices. ICCE-TW 2022: 79-80
[c15]
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Jian-Hsing Lee, Yeh-Jen Huang, Li-Yang Hong, Li-Fan Chen, Yeh-Ning Jou, Shin-Cheng Lin, Walter Wohlmuth, Chih-Cherng Liao, Ching-Ho Li, Shoa-Chang Huang, Ke-Horng Chen:
Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection. IRPS 2022: 2
2021
[c14]
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Shao-Chang Huang, Yu-Yung Kao, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Kai-Chieh Hsu, Gong-Kai Lin, Jian-Hsing Lee, Ke-Horng Chen:
Signal Control Switching Applied on Large Array Devices' Layouts. ICCE-TW 2021: 1-2
[c13]
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Shao-Chang Huang, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Kai-Chieh Hsu, Gong-Kai Lin, Jian-Hsing Lee:
Optimizing Power IC Layouts by Simulation Tools. ICCE-TW 2021: 1-2
[c12]
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  - conf/irps/ChenLNBLK21
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Chao-Yang Chen, Jian-Hsing Lee, Karuna Nidhi, Tzer-Yaa Bin, Geeng-Lih Lin, Ming-Dou Ker:
Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process. IRPS 2021: 1-4
2020
[c11]
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Shao-Chang Huang, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Ting-You Lin, Kai-Chieh Hsu, Gong-Kai Lin, Jian-Hsing Lee, Yu-Yung Kao, Ke-Horng Chen:
The Correlations between ESD and TLP in Large Array Devices. ICCE-TW 2020: 1-2
[c10]
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Shao-Chang Huang, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Ting-You Lin, Kai-Chieh Hsu, Gong-Kai Lin, Chih-Hsuan Lin, Jian-Hsing Lee, Yu-Yung Kao, Ke-Horng Chen:
Signal Control Switching for Improving Large Array Devices' ESD Performances. ICCE-TW 2020: 1-2

2010 – 2019

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2019
[c9]
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Shao-Chang Huang, Chih-Cherng Liao, Hsien-Feng Liao, Shou-Peng Weng, Karuna Nidhi, Yu-Kai Wang, Yi-Jen Chen, Hwa-Chyi Chiou, Yeh-Ning Jou, Jian-Hsing Lee:
Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances. ICCE-TW 2019: 1-2
[c8]
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  - conf/irps/LeeI19
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Jian-Hsing Lee, Natarajan Mahadeva Iyer:
Tunable Holding-Voltage High Voltage ESD Devices. IRPS 2019: 1-8
[c7]
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Jian-Hsing Lee, Natarajan Mahadeva Iyer, Timothy J. Maloney:
Physical Model for ESD Human Body Model to Transmission Line Pulse. IRPS 2019: 1-7
2015
[c6]
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  - conf/irps/LeeTPN15
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Jian-Hsing Lee, Kunihiko Takahashi, Manjunatha Prabhu, Mahadeva Iyer Natarajan:
Printed-circuit board (PCB) charge induced product yield-loss during the final test. IRPS 2015: 2
[c5]
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  - conf/irps/LeePKSNP15
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Jian-Hsing Lee, Manjunatha Prabhu, Konstantin Korablev, Jagar Singh, Mahadeva Iyer Natarajan, Shesh Mani Pandey:
Methodology to achieve planar technology-like ESD performance in FINFET process. IRPS 2015: 3
[c4]
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  - conf/irps/KaoLCLLHHS15
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Tzu-Cheng Kao, Chen-Hsin Lien, Chien-Wei Chiu, Jian-Hsing Lee, Yen-Hsiang Lo, Chung-Yu Hung, Tsung-Yi Huang, Hung-Der Su:
Robust ESD self-protected LDNMOSFET by an enhanced displacement-current triggering. IRPS 2015: 5
[c3]
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  - conf/irps/KaoLLWTS15
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Tzu-Cheng Kao, Jian-Hsing Lee, Chen-Hsin Lien, Chih-Hsien Wang, Kuang-Cheng Tai, Hung-Der Su:
Enhanced CDM-robustness for the packaged IC with the extra bonding wire to the die-attach plate. IRPS 2015: 6

2000 – 2009

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2005
[c2]
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  - conf/iscas/LeeSWYO05
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Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Kuo-Feng Yu, Tong-Chern Ong:
A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O. ISCAS (2) 2005: 1198-1201
2002
[c1]
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  - conf/cicc/LeeWPCYO02
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Jian-Hsing Lee, Yi-Hsun Wu, K. R. Peng, R. Y. Chang, Talee Yu, Tong-Chern Ong:
The embedded SCR NMOS and low capacitance ESD protection device. CICC 2002: 93-96

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