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Emil Gizdarski
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2010 – 2019
- 2017
- [c16]Emil Gizdarski, Peter Wohl, John A. Waicukauski:
A New Paradigm for Synthesis of Linear Decompressors. DAC 2017: 39:1-39:6 - 2014
- [c15]Emil Gizdarski:
Two-Step Dynamic Encoding for Linear Decompressors. ATS 2014: 330-335 - [c14]Xiaolei Cai, Emil Gizdarski, Dan Landau:
A shared memory based parallel diagnosis system. VTS 2014: 1-6 - 2011
- [j6]Emil Gizdarski:
Construction and Analysis of Augmented Time Compactors. J. Electron. Test. 27(2): 109-122 (2011) - 2010
- [c13]Peter Wohl, John A. Waicukauski, Frederic Neuveux, Emil Gizdarski:
Fully X-tolerant, very high scan compression. DAC 2010: 362-367 - [c12]Emil Gizdarski:
Constructing augmented time compactors. ETS 2010: 151-156
2000 – 2009
- 2008
- [c11]Emil Gizdarski:
Constructing Augmented Multimode Compactors. VTS 2008: 29-34 - 2007
- [c10]Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini:
Minimizing the Impact of Scan Compression. VTS 2007: 67-74 - 2005
- [c9]Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew:
Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. VTS 2005: 359-365 - 2004
- [j5]Davide Appello
, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew:
Understanding Yield Losses in Logic Circuits. IEEE Des. Test Comput. 21(3): 208-215 (2004) - [c8]Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams:
Changing the Scan Enable during Shift. VTS 2004: 73-78 - [c7]Davide Appello
Yield Analysis of Logic Circuits. VTS 2004: 103-108 - 2003
- [c6]Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams:
A Reconfigurable Shared Scan-in Architecture. VTS 2003: 9-14 - 2002
- [j4]Michiko Inoue, Emil Gizdarski, Hideo Fujiwara:
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. J. Electron. Test. 18(1): 55-62 (2002) - [j3]Emil Gizdarski, Hideo Fujiwara:
SPIRIT: a highly robust combinational test generation algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1446-1458 (2002) - [c5]Emil Gizdarski, Hideo Fujiwara:
Fault Set Partition for Efficient Width Compression. Asian Test Symposium 2002: 194-199 - 2001
- [c4]Emil Gizdarski, Hideo Fujiwara:
A Framework for Low Complexity Static Learning. DAC 2001: 546-549 - [c3]Emil Gizdarski, Hideo Fujiwara:
SPIRIT: A Highly Robust Combinational Test Generation Algorithm. VTS 2001: 346-351 - 2000
- [j2]Emil Gizdarski:
Detection of Delay Faults in Memory Address Decoders. J. Electron. Test. 16(4): 381-387 (2000) - [c2]Emil Gizdarski, Hideo Fujiwara:
Spirit: satisfiability problem implementation for redundancy identification and test generation. Asian Test Symposium 2000: 171-178 - [c1]Michiko Inoue, Emil Gizdarski, Hideo Fujiwara:
A class of sequential circuits with combinational test generation complexity under single-fault assumption. Asian Test Symposium 2000: 398-403
1990 – 1999
- 1996
- [j1]Emil Gizdarski:
Built-in self-test for folded bit-line Mbit DRAMs. Integr. 21(1-2): 95-112 (1996)
Coauthor Index
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