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Chih-Yen Lo
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2020 – today
- 2020
- [c15]Tsung-Fu Hsieh, Jin-Fu Li, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method. ITC-Asia 2020: 41-46
2010 – 2019
- 2018
- [c14]Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A channel-sharable built-in self-test scheme for multi-channel DRAMs. ASP-DAC 2018: 245-250 - [c13]Jia-Yun Hu, Kuan-Wei Hou, Chih-Yen Lo, Yung-Fa Chou, Cheng-Wen Wu
:
RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction. ITC-Asia 2018: 19-24 - 2017
- [c12]Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. ITC-Asia 2017: 107-111 - 2016
- [c11]Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories. ATS 2016: 281-286 - [c10]Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. ITC 2016: 1-7 - 2015
- [j3]Che-Wei Chou, Jin-Fu Li, Yun-Chao Yu, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Hierarchical Test Integration Methodology for 3-D ICs. IEEE Des. Test 32(4): 59-70 (2015) - [c9]Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A hybrid built-in self-test scheme for DRAMs. VLSI-DAT 2015: 1-4 - 2014
- [c8]Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. ATS 2014: 1-6 - [c7]Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo:
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. ATS 2014: 143-148 - 2013
- [c6]Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
An FPGA-based test platform for analyzing data retention time distribution of DRAMs. VLSI-DAT 2013: 1-4 - [c5]Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. VTS 2013: 1-6 - 2012
- [c4]Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A built-in self-test scheme for 3D RAMs. ITC 2012: 1-9 - 2010
- [j2]Chih-Yen Lo, Yu-Tsao Hsing
SOC Test Architecture and Method for 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1645-1649 (2010)
2000 – 2009
- 2009
- [c3]Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu
Test Integration for SOC Supporting Very Low-Cost Testers. Asian Test Symposium 2009: 287-292 - 2007
- [j1]Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu
STEAC: A Platform for Automatic SOC Test Integration. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 541-545 (2007) - 2006
- [c2]Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
A network security processor design based on an integrated SOC design and test platform. DAC 2006: 490-495 - 2004
- [c1]Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee:
An SOC Test Integration Platform and Its Industrial Realization. ITC 2004: 1213-1222
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