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Luis A. Camuñas-Mesa
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2020 – today
- 2024
- [j13]Hamidreza Erfanijazi
, Luis A. Camuñas-Mesa
A Fully Digital Relaxation-Aware Analog Programming Technique for HfOx RRAM Arrays. IEEE Trans. Circuits Syst. II Express Briefs 71(8): 3685-3689 (2024) - [c24]Luis A. Camuñas-Mesa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Mismatch calibration strategy for query-driven AER read-out in a memristor-CMOS neuromorphic chip. ISCAS 2024: 1-5 - 2023
- [j12]Luis A. Camuñas-Mesa
Combining Software-Defined Radio Learning Modules and Neural Networks for Teaching Communication Systems Courses. Inf. 14(11): 599 (2023) - [j11]Promise I. Enwere, Encarnación Cervantes-Requena, Luis A. Camuñas-Mesa, José M. de la Rosa:
Using ANNs to predict the evolution of spectrum occupancy in cognitive-radio systems. Integr. 93: 102070 (2023) - [j10]Sarah A. El-Sayed, Theofilos Spyrou
Compact Functional Testing for Neuromorphic Computing Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2391-2403 (2023) - [c23]Isabel Ortíz-Ramírez, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona:
Study of foveation mechanisms in Dynamic Vision Sensors. DCIS 2023: 1-6 - [c22]Ivan Diez-de-los-Rios
A multi-core memristor chip for Stochastic Binary STDP. ISCAS 2023: 1-5 - [i4]Hamid Reza Erfani Jazi, Luis A. Camuñas-Mesa, Elisa Vianello, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
A Fully Digital Relaxation-Aware Analog Programming Technique for HfOx RRAM Arrays. CoRR abs/2301.08516 (2023) - 2022
- [j9]Luis A. Camuñas-Mesa
A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 898-912 (2022) - [c21]Theofilos Spyrou, Sarah A. El-Sayed, Engin Afacan, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. Stratigopoulos:
Reliability Analysis of a Spiking Neural Network Hardware Accelerator. DATE 2022: 370-375 - [c20]Promise I. Okorie, Luis A. Camuñas-Mesa, José M. de la Rosa:
Using ANNs to Predict Frequency Spectrum Occupancy in Cognitive-Radio Receivers. DCIS 2022: 1-5 - [i3]Luis A. Camuñas-Mesa, Elisa Vianello, Carlo Reita, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP. CoRR abs/2209.06068 (2022) - 2021
- [j8]Charanraj Mohan
Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration. IEEE Access 9: 38043-38061 (2021) - [c19]Theofilos Spyrou, Sarah A. El-Sayed, Engin Afacan, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. Stratigopoulos:
Neuron Fault Tolerance in Spiking Neural Networks. DATE 2021: 743-748 - [c18]Hassan Aboushady, Alhassan Sayed, Luis A. Camuñas-Mesa, José M. de la Rosa:
Cognitive Radio Circuits and Systems - Application to Digitizers. ISCAS 2021: 1-5 - [c17]C. Mohan, Luis A. Camuñas-Mesa, José M. de la Rosa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Implementation of Binary Stochastic STDP Learning Using Chalcogenide-Based Memristive Devices. ISCAS 2021: 1-5 - [i2]C. Mohan, Luis A. Camuñas-Mesa, José M. de la Rosa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices. CoRR abs/2103.01271 (2021) - [i1]Charanraj Mohan, Luis A. Camuñas-Mesa, Elisa Vianello, Carlo Reita, José M. de la Rosa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Experimental Body-input Three-stage DC offset Calibration Scheme for Memristive Crossbar. CoRR abs/2103.02651 (2021) - 2020
- [c16]Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona:
Implementation of a tunable spiking neuron for STDP with memristors in FDSOI 28nm. AICAS 2020: 94-98 - [c15]Virginia Zúñiga-González
Using Neural Networks for Optimum band selection in Cognitive-Radio Systems. ICECS 2020: 1-4 - [c14]Sarah A. El-Sayed, Theofilos Spyrou, Antonios Pavlidis, Engin Afacan, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. D. Stratigopoulos:
Spiking Neuron Hardware-Level Fault Modeling. IOLTS 2020: 1-4 - [c13]Tobi Delbrück, Ibrahim Abe M. Elfadel, Shahzad Muzaffar, Germain Haessig, Bo Wang
Lessons Learned the Hard Way. ISCAS 2020: 1-18 - [c12]Charanraj Mohan
Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar. ISCAS 2020: 1-5 - [c11]Gordana Jovanovic-Dolecek
Low Order Wideband Multiplierless Comb Compensator. MWSCAS 2020: 162-165
2010 – 2019
- 2019
- [c10]Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona:
Low-power hardware implementation of SNN with decision block for recognition tasks. ICECS 2019: 73-76 - [c9]Sarah A. El-Sayed, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. D. Stratigopoulos:
Self-Testing Analog Spiking Neuron Circuit. SMACD 2019: 81-84 - 2018
- [j7]Luis A. Camuñas-Mesa
Event-Driven Stereo Visual Tracking Algorithm to Solve Object Occlusion. IEEE Trans. Neural Networks Learn. Syst. 29(9): 4223-4237 (2018) - [c8]Luis A. Camuñas-Mesa, Y. Domínguez-Cordero, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA. ISCAS 2018: 1-5 - 2014
- [c7]Luis A. Camuñas-Mesa
Live demonstration: Event-driven sensing and processing for high-speed robotic vision. BioCAS 2014: 183 - [c6]Luis A. Camuñas-Mesa
Event-driven sensing and processing for high-speed robotic vision. BioCAS 2014: 516-519 - [c5]Luis A. Camuñas-Mesa
Event-driven stereo vision with orientation filters. ISCAS 2014: 257-260 - 2013
- [j6]Luis A. Camuñas-Mesa
A Detailed and Fast Model of Extracellular Recordings. Neural Comput. 25(5): 1191-1212 (2013) - 2012
- [j5]Luis A. Camuñas-Mesa
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors. IEEE J. Solid State Circuits 47(2): 504-517 (2012) - 2011
- [j4]Luis A. Camuñas-Mesa
A 32, times, 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(4): 777-790 (2011) - 2010
- [j3]José Antonio Pérez-Carrasco
Fast vision through frameless event-based sensing and convolutional processing: application to texture recognition. IEEE Trans. Neural Networks 21(4): 609-620 (2010) - [c4]Luis A. Camuñas-Mesa
Neocortical frame-free vision sensing and processing through scalable Spiking ConvNet hardware. IJCNN 2010: 1-8 - [c3]Luis A. Camuñas-Mesa
On scalable spiking convnet hardware for cortex-like visual sensory processing systems. ISCAS 2010: 249-252
2000 – 2009
- 2009
- [j2]Rafael Serrano-Gotarredona, Matthias Oster, Patrick Lichtsteiner, Alejandro Linares-Barranco
CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing- Learning-Actuating System for High-Speed Visual Object Recognition and Tracking. IEEE Trans. Neural Networks 20(9): 1417-1438 (2009) - 2008
- [c2]Luis A. Camuñas-Mesa
Fully digital AER convolution chip for vision processing. ISCAS 2008: 652-655 - 2007
- [j1]Rafael Serrano-Gotarredona, Luis A. Camuñas-Mesa
The Stochastic I-Pot: A Circuit Block for Programming Bias Currents. IEEE Trans. Circuits Syst. II Express Briefs 54-II(9): 760-764 (2007) - 2004
- [c1]Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, Rafael Serrano-Gotarredona, Luis A. Camuñas:
On leakage current temperature characterization using sub-pico-ampere circuit techniques. ISCAS (1) 2004: 361-364
Coauthor Index
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last updated on 2024-09-10 01:07 CEST by the dblp team
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