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Koji Nii
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2020 – today
- 2024
- [j39]Yumito Aoyagi
, Koji Nii
A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. IEEE J. Solid State Circuits 59(4): 1225-1234 (2024) - [c53]Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang
15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. ISSCC 2024: 280-282 - [c52]Tomotaka Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Koji Nii, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j38]Yoshisato Yokoyama
Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing. IEEE J. Solid State Circuits 58(7): 2098-2108 (2023) - [c51]Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka
A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. VLSI Technology and Circuits 2023: 1-2 - [c50]Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. VLSI Technology and Circuits 2023: 1-2 - 2021
- [j37]Yoshisato Yokoyama
Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1495-1499 (2021) - 2020
- [c49]Koji Nii, Yasuhiro Taniguchi, Kosuke Okuyama:
A Cost-Effective Embedded Nonvolatile Memory with Scalable LEE Flash®-G2 SONOS for Secure IoT and Computing-in-Memory (CiM) Applications. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [j36]Masanori Hayashikoshi, Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Kiyoshi Kawabata, Koji Nii, Hideyuki Noda, Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka:
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications. IEICE Trans. Electron. 102-C(4): 287-295 (2019) - [j35]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - 2018
- [j34]Kan Takeuchi, Masaki Shimada, Takeshi Okagaki, Koji Shibutani, Koji Nii, Fumio Tsuchiya:
Wear-out stress monitor utilising temperature and voltage sensitive ring oscillators. IET Circuits Devices Syst. 12(2): 182-188 (2018) - [j33]Masanori Hayashikoshi
Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications. IEEE Trans. Multi Scale Comput. Syst. 4(4): 784-792 (2018) - [j32]Makoto Yabuuchi
A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2335-2344 (2018) - [c48]Yoshisato Yokoyama, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Makoto Yabuuchi, Yuichiro Ishii, Koji Nii:
40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications. A-SSCC 2018: 9-12 - [c47]Mitsuhiko Igarashi
A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process. A-SSCC 2018: 195-196 - [c46]Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Yasumasa Tsukamoto, Koji Shibutani, Koji Nii:
Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET. IRPS 2018: 1 - [c45]Makoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka:
12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM. VLSI Circuits 2018: 19-20 - 2017
- [j31]Krishnendu Chakrabarty
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [c44]Yoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii:
A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode. A-SSCC 2017: 13-16 - [c43]Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Koji Nii, Hiroyuki Kondo:
Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications. COOL Chips 2017: 1-3 - 2016
- [j30]Takao Nomura, Ryo Mori, Koji Takayanagi, Kazuki Fukuoka, Koji Nii:
Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 364-372 (2016) - [j29]Haruki Mori, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi
A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor. IEICE Trans. Electron. 99-C(8): 901-908 (2016) - [c42]Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii:
A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. A-SSCC 2016: 17-20 - [c41]Kan Takeuchi, Masaki Shimada, Takeshi Okagaki, Koji Shibutani, Koji Nii, Fumio Tsuchiya:
FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUs. ESSCIRC 2016: 265-268 - [c40]Makoto Yabuuchi, Yohei Sawada, Toshiaki Sano, Yuichiro Ishii, Shinji Tanaka, Miki Tanaka, Koji Nii:
A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time. VLSI Circuits 2016: 1-2 - 2015
- [j28]Mitsuhiko Igarashi
A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores. IEEE J. Solid State Circuits 50(1): 92-101 (2015) - [j27]Takuya Sawada, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata
An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2347-2351 (2015) - [c39]Yoshisato Yokoyama, Yuichiro Ishii, Toshihiro Inada, Koji Tanaka, Miki Tanaka, Yoshiki Tsujihashi, Koji Nii:
A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU. A-SSCC 2015: 1-4 - [c38]Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. CICC 2015: 1-4 - [c37]Mitsuhiko Igarashi
An on-die digital aging monitor against HCI and xBTI in 16 nm Fin-FET bulk CMOS technology. ESSCIRC 2015: 112-115 - [c36]Tadaaki Yamauchi, Hiroyuki Kondo, Koji Nii:
Automotive low power technology for IoT society. VLSIC 2015: 80- - [c35]Yasumasa Tsukamoto, Masao Morimoto, Makoto Yabuuchi, Miki Tanaka, Koji Nii:
1.8 Mbit/mm2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology. VLSIC 2015: 274- - 2014
- [j26]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. IEICE Trans. Electron. 97-C(4): 332-341 (2014) - [j25]Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa:
28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 575-584 (2014) - [c34]Yoshisato Yokoyama, Yuichiro Ishii, Koji Tanaka, Tatsuya Fukuda, Yoshiki Tsujihashi, Atsushi Miyanishi, Shinobu Asayama, Keiichi Maekawa, Kazutoshi Shiba, Koji Nii:
40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues. A-SSCC 2014: 25-28 - [c33]Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda:
The LSI implementation of a memory based field programmable device for MCU peripherals. DDECS 2014: 183-188 - [c32]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. ISQED 2014: 16-23 - [c31]Yoshisato Yokoyama, Yuichiro Ishii, Hidemitsu Kojima, Atsushi Miyanishi, Yoshiki Tsujihashi, Shinobu Asayama, Kazutoshi Shiba, Koji Tanaka, Tatsuya Fukuda, Koji Nii, Kazumasa Yanagisawa:
40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU. ISQED 2014: 24-31 - [c30]Hidehiro Fujiwara, Makoto Yabuuchi, Koji Nii:
Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS. ISQED 2014: 523-528 - [c29]Mitsuhiko Igarashi
10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores. ISSCC 2014: 178-179 - [c28]Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii:
13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists. ISSCC 2014: 234-235 - [c27]Koji Nii, Teruhiko Amano, Naoya Watanabe, Minoru Yamawaki, Kenji Yoshinaga, Mihoko Wada, Isamu Hayashi:
13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM. ISSCC 2014: 240-241 - [c26]Shinji Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Toshiaki Sano, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato:
A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. VLSIC 2014: 1-2 - 2013
- [j24]Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi
Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(7): 1579-1585 (2013) - [j23]Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki:
A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS. IEEE J. Solid State Circuits 48(4): 917-923 (2013) - [j22]Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai:
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. IEEE J. Solid State Circuits 48(11): 2671-2680 (2013) - [j21]Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Takeshi Kataoka, Toshihiro Hattori:
Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor. IEEE Micro 33(6): 26-36 (2013) - [c25]Koji Nii, Toshiaki Kirihata:
Advanced memory topics. CICC 2013: 1 - [c24]Takao Nomura, Ryo Mori, Munehiro Ito, Koji Takayanagi, Toshihiko Ochiai, Kazuki Fukuoka, Kazuo Otsuga, Koji Nii, Sadayuki Morita, Tomoaki Hashimoto, Tsuyoshi Kida, Junichi Yamada, Hideki Tanaka:
Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor. CICC 2013: 1-4 - [c23]Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Miki Tanaka, Shinji Tanaka, Koji Nii:
A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure. CICC 2013: 1-4 - [c22]Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda:
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. ISQED 2013: 438-441 - [c21]Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori:
A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor. ISSCC 2013: 156-157 - 2012
- [j20]Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata
Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation. IEICE Trans. Electron. 95-C(4): 586-593 (2012) - [j19]Shusuke Yoshimoto
Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(8): 1359-1365 (2012) - [c20]Koji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara, Kazuyoshi Okamoto:
A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. Asian Test Symposium 2012: 246-251 - [c19]Kazuki Fukuoka, Ryo Mori, A. Kato, Motoshige Igarashi, Koji Shibutani, T. Yamaki, Shinji Tanaka, Koji Nii, Sadayuki Morita, Takao Koike, Noriaki Sakamoto:
A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology. CICC 2012: 1-4 - [c18]Yasumasa Tsukamoto, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Changhwan Shin, Tsu-Jae King Liu:
Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application. ISQED 2012: 270-274 - [c17]Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki:
A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. ISSCC 2012: 236-238 - [c16]Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii:
A stable chip-ID generating physical uncloneable function using random address errors in SRAM. SoCC 2012: 143-147 - 2011
- [j18]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. Inf. Media Technol. 6(2): 296-306 (2011) - [j17]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. IPSJ Trans. Syst. LSI Des. Methodol. 4: 80-90 (2011) - [j16]Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, Kazumasa Yanagisawa:
A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. IEEE J. Solid State Circuits 46(11): 2535-2544 (2011) - [c15]Yasumasa Tsukamoto, Takeshi Kida, T. Yamaki, Yuichiro Ishii, Koji Nii, Koji Tanaka, Shinji Tanaka, Yuji Kihara:
Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs. CICC 2011: 1-4 - [c14]Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Kazuyoshi Okamoto, Kazutaka Mori, Kazumasa Yanagisawa:
A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias. CICC 2011: 1-4 - [c13]Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Shigeki Tawa, Koji Maekawa, Motoshige Igarashi, Koji Nii:
A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. ISLPED 2011: 285-290 - 2010
- [c12]Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara:
A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias. ISSCC 2010: 356-357 - [c11]Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto:
Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. SoCC 2010: 519-524
2000 – 2009
- 2009
- [j15]Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara:
Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. IEEE J. Solid State Circuits 44(3): 977-986 (2009) - [c10]Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED 2009: 659-663 - 2008
- [j14]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Trans. Electron. 91-C(4): 543-552 (2008) - [j13]Masako Fujii, Koji Nii, Hiroshi Makino, Shigeki Ohbayashi, Motoshige Igarashi, Takeshi Kawamura, Miho Yokota, Nobuhiro Tsuda, Tomoaki Yoshizawa, Toshikazu Tsutsui, Naohiko Takeshita, Naofumi Murata, Tomohiro Tanaka, Takanari Fujiwara, Kyoko Asahina, Masakazu Okada, Kazuo Tomita, Masahiko Takeuchi, Shigehisa Yamamoto, Hiromitsu Sugimoto, Hirofumi Shinohara:
A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology. IEICE Trans. Electron. 91-C(8): 1338-1347 (2008) - [j12]Hirofumi Shinohara, Koji Nii, Hidetoshi Onodera:
Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration. IEICE Trans. Electron. 91-C(9): 1488-1500 (2008) - [j11]Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE J. Solid State Circuits 43(1): 96-108 (2008) - [j10]Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara:
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. IEEE J. Solid State Circuits 43(1): 180-191 (2008) - [j9]Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu:
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. IEEE J. Solid State Circuits 43(4): 938-945 (2008) - [j8]Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 620-627 (2008) - 2007
- [j7]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. IEICE Trans. Electron. 90-C(10): 1949-1956 (2007) - [j6]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi
Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2695-2702 (2007) - [j5]Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE J. Solid State Circuits 42(4): 820-829 (2007) - [c9]Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara:
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. ISSCC 2007: 326-606 - [c8]Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. ISSCC 2007: 488-617 - [c7]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ISVLSI 2007: 107-112 - 2006
- [j4]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi
A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3634-3641 (2006) - [j3]Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. IEEE J. Solid State Circuits 41(3): 705-711 (2006) - [c6]Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66 - 2005
- [c5]Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. ICCAD 2005: 398-405 - [c4]Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino:
A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. ISCAS (1) 2005: 73-76 - 2004
- [j2]Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade:
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. IEEE J. Solid State Circuits 39(4): 684-693 (2004)
1990 – 1999
- 1998
- [c3]Koji Nii, Hiroshi Makino, Yoshiki Tsujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano:
A low power SRAM using auto-backgate-controlled MT-CMOS. ISLPED 1998: 293-298 - 1995
- [j1]Koji Nii, Hideshi Maeno, Tokuya Osawa, Shuhei Iwade, Shinpei Kayano, Hiroshi Shibata:
A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates. IEEE J. Solid State Circuits 30(3): 316-320 (1995) - 1992
- [c2]Hideshi Maeno, Koji Nii
LSSD Compatible and Concurrently Testable Ram. ITC 1992: 608-614 - 1990
- [c1]Masaki Hashizume, Takeomi Tamesada, Koji Nii:
A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory level. ICCD 1990: 24-28
Coauthor Index
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