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Andrew Lines
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2020 – today
- 2021
- [c12]Andrew Lines:
Asynchronous Serial Infrastructure Using FPIO. ASYNC 2021: 62-63
2010 – 2019
- 2018
- [j4]Mike Davies, Narayan Srinivasa, Tsung-Han Lin, Gautham N. Chinya, Yongqiang Cao, Sri Harsha Choday, Georgios D. Dimou, Prasad Joshi, Nabil Imam, Shweta Jain, Yuyun Liao, Chit-Kwan Lin, Andrew Lines, Ruokun Liu, Deepak Mathaikutty, Steven McCoy, Arnab Paul, Jonathan Tse, Guruguhanathan Venkataramanan, Yi-Hsin Weng, Andreas Wild, Yoonseok Yang, Hong Wang:
Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. IEEE Micro 38(1): 82-99 (2018) - [c11]Andrew Lines, Prasad Joshi, Ruokun Liu, Steve McCoy, Jonathan Tse, Yi-Hsin Weng, Mike Davies:
Loihi Asynchronous Neuromorphic Research Chip. ASYNC 2018: 32-33 - [c10]Suhwan Kim, Vaibhav A. Vaidya, Christopher Schaef, Andrew Lines, Harish Krishnamurthy, Sheldon Weng, Xiaosen Liu, Dileep Kurian, Tanay Karnik, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes. VLSI Circuits 2018: 195-196 - 2014
- [j3]Georgios D. Dimou, Peter A. Beerel, Andrew Lines:
Performance-Driven Clustering of Asynchronous Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 197-209 (2014) - [c9]Mike Davies, Andrew Lines, Jon Dama, Alain Gravel, Robert Southworth, Georgios D. Dimou, Peter A. Beerel:
A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design. ASYNC 2014: 103-104 - 2013
- [c8]Jonathan Tse, Andrew Lines:
NanoMesh: An Asynchronous Kilo-Core System-on-Chip. ASYNC 2013: 40-49 - 2011
- [j2]Peter A. Beerel, Georgios D. Dimou, Andrew Lines:
Proteus: An ASIC Flow for GHz Asynchronous Designs. IEEE Des. Test Comput. 28(5): 36-51 (2011) - [c7]Georgios D. Dimou, Peter A. Beerel, Andrew Lines:
Performance-Driven Clustering of Asynchronous Circuits. PATMOS 2011: 92-101
2000 – 2009
- 2009
- [c6]Jonathan Dama, Andrew Lines:
GHz Asynchronous SRAM in 65nm. ASYNC 2009: 85-94 - 2007
- [c5]Andrew Lines:
The Vortex: A Superscalar Asynchronous Processor. ASYNC 2007: 39-48 - 2006
- [c4]Peter A. Beerel, Nam-Hoon Kim, Andrew Lines, Mike Davies:
Slack Matching Asynchronous Designs. ASYNC 2006: 184-194 - 2004
- [j1]Andrew Lines:
Asynchronous Interconnect for Synchronous SoC Design. IEEE Micro 24(1): 32-41 (2004) - 2003
- [c3]Andrew Lines:
Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs. Hot Interconnects 2003: 2-9
1990 – 1999
- 1997
- [c2]Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul I. Pénzes, Robert Southworth, Uri Cummings:
The Design of an Asynchronous MIPS R3000 Microprocessor. ARVLSI 1997: 164-181 - 1994
- [c1]Uri Cummings, Andrew Lines, Alain J. Martin:
An asynchronous pipelined lattice structure filter. ASYNC 1994: 126-133
Coauthor Index
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