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Deepak Dasalukunte
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2020 – today
- 2024
- [c10]Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Niranjan Gowda, Brent R. Carlton:
A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j8]Hechen Wang
, Renzhi Liu
A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference. IEEE J. Solid State Circuits 58(4): 1037-1050 (2023) - [j7]Richard Dorrance
An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET. IEEE J. Solid State Circuits 58(10): 2826-2838 (2023) - 2022
- [c9]Hechen Wang
A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. VLSI Technology and Circuits 2022: 36-37 - [i1]Andrey Belogolovy, Deepak Dasalukunte, Richard Dorrance, Evgeny Stupachenko, Xue Zhang:
Low latency communication over commercially available LTE and remote driving. CoRR abs/2209.09794 (2022) - 2021
- [j6]Deepak Dasalukunte
A Vector Processor for Mean Field Bayesian Channel Estimation. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1348-1359 (2021) - 2020
- [j5]Renzhi Liu
An 802.11ba-Based Wake-Up Radio Receiver With Wi-Fi Transceiver Integration. IEEE J. Solid State Circuits 55(5): 1151-1164 (2020)
2010 – 2019
- 2019
- [c8]Richard Dorrance
An Ultra-Low Power, Fully Integrated Wake-Up Receiver and Digital Baseband with All-Digital Impairment Correction and -92.4dBm Sensitivity for 802.11ba. VLSI Circuits 2019: 80- - 2017
- [c7]Farhana Sheikh
Adaptive and multi-mode baseband systems for next generation wireless communication. ACSSC 2017: 1499-1503 - 2013
- [j4]Deepak Dasalukunte, Fredrik Rusek, Viktor Öwall:
An 0.8-mm2 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS. IEEE J. Solid State Circuits 48(7): 1680-1688 (2013) - [j3]Shahid Mehmood, Deepak Dasalukunte, Viktor Öwall:
Hardware Architecture of IOTA Pulse Shaping Filters for Multicarrier Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(3): 733-742 (2013) - 2012
- [c6]Deepak Dasalukunte, Fredrik Rusek, Viktor Öwall:
A 0.8 mm2 9.6 mW implementation of a multicarrier Faster-than-Nyquist signaling iterative decoder in 65nm CMOS. ESSCIRC 2012: 173-176 - 2011
- [j2]Deepak Dasalukunte, Fredrik Rusek, Viktor Öwall:
Multicarrier Faster-Than-Nyquist Transceivers: Hardware Architecture and Performance Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(4): 827-838 (2011) - [c5]Deepak Dasalukunte, Fredrik Rusek, Viktor Öwall:
Improved Memory Architecture for Multicarrier Faster-than-Nyquist Iterative Decoder. ISVLSI 2011: 296-300 - [c4]Deepak Dasalukunte, Fredrik Rusek, John B. Anderson, Viktor Öwall:
Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier Systems. ISVLSI 2011: 359-360 - [c3]Deepak Dasalukunte, Shahid Mehmood, Viktor Öwall:
Complexity analysis of IOTA filter architectures in faster-than-Nyquist multicarrier systems. NORCHIP 2011: 1-4 - 2010
- [c2]Deepak Dasalukunte, Fredrik Rusek, Viktor Öwall:
An Iterative Decoder for Multicarrier Faster-Than-Nyquist Signaling Systems. ICC 2010: 1-5
2000 – 2009
- 2009
- [c1]Deepak Dasalukunte, Fredrik Rusek, John B. Anderson, Viktor Öwall:
Transmitter Architecture for Faster-than-Nyquist Signaling Systems. ISCAS 2009: 1028-1031 - 2008
- [j1]Dominique Noguet, Marc Laugeois, Xavier Popon, B. Balamuralidhar, Manuel Lobeira, Narasimha Sortur, Deepak Dasalukunte, Cedric Dehos, Zeta Bakirtzoglou:
An MC-SS Platform for Short-Range Communications in the Personal Network Context. EURASIP J. Wirel. Commun. Netw. 2008 (2008)
Coauthor Index
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