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Ding-Yong Hong
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2020 – today
- 2024
- [c26]Chi-Yu Chiu, Ding-Yong Hong, Pangfeng Liu, Jan-Jan Wu:
Effective Compression of Language Models by Combining Pruning and Knowledge Distillation. COMPSAC 2024: 429-438 - 2023
- [c25]Chien-Hung Lin, Ding-Yong Hong, Pangfeng Liu, Jan-Jan Wu:
Accelerate Inference of CNN Models on CPU via Column Combining Based on Simulated Annealing. candar 2023: 20-29 - [c24]Chao-Yu Lee, Ding-Yong Hong, Pangfeng Liu, Jan-Jan Wu:
Function Clustering to Optimize Resource Utilization on Container Platform. ICPADS 2023: 2724-2725 - [c23]Cheng-Hung Wu, Ding-Yong Hong, Pangfeng Liu, Jan-Jan Wu:
Exploiting Fine-Grained Structured Pruning for Efficient Inference on CNN Model. ICPADS 2023: 2835-2836 - 2022
- [j10]Hong-Xuan Wei, Pangfeng Liu, Ding-Yong Hong, Jan-Jan Wu, An-Tai Chen:
CNN Models Acceleration Using Filter Pruning and Sparse Tensor Core. Int. J. Netw. Comput. 12(2): 270-294 (2022) - [j9]Horng-Ruey Huang, Ding-Yong Hong, Jan-Jan Wu, Kung-Fu Chen, Pangfeng Liu, Wei-Chung Hsu:
Accelerating Video Captioning on Heterogeneous System Architectures. ACM Trans. Archit. Code Optim. 19(3): 38:1-38:25 (2022) - [c22]Yu-Jen Chang, Ding-Yong Hong, Pangfeng Liu, Jan-Jan Wu:
Efficient Inference on Convolutional Neural Networks by Image Difficulty Prediction. IEEE Big Data 2022: 5672-5681 - [c21]Kuan-Wei Lu, Pangfeng Liu, Ding-Yong Hong, Jan-Jan Wu:
Efficient Dual Batch Size Deep Learning for Distributed Parameter Server Systems. COMPSAC 2022: 630-639 - [c20]Kung-Fu Chen, Ding-Yong Hong:
Rewriting Deep Learning Models for Maximizing Edge TPU Utilization. ICPADS 2022: 657-664 - [c19]Yi You, Pangfeng Liu, Ding-Yong Hong, Jan-Jan Wu, Wei-Chung Hsu:
Accelerating Convolutional Neural Networks via Inter-operator Scheduling. ICPADS 2022: 916-923 - 2021
- [c18]Chang-Han Chiang, Pangfeng Liu, Da-Wei Wang, Ding-Yong Hong, Jan-Jan Wu:
Optimal Branch Location for Cost-effective Inference on Branchynet. IEEE BigData 2021: 5071-5080 - [c17]An-Tai Chen, Pangfeng Liu, Ding-Yong Hong, Jan-Jan Wu:
Accelerate CNN Models via Filter Pruning and Sparse Tensor Core. CANDAR 2021: 1-9 - [c16]Horng-Ruey Huang, Ding-Yong Hong, Jan-Jan Wu, Pangfeng Liu, Wei-Chung Hsu:
Efficient Video Captioning on Heterogeneous System Architectures. IPDPS 2021: 1035-1045
2010 – 2019
- 2019
- [j8]Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translator. J. Syst. Archit. 98: 173-190 (2019) - [j7]Ding-Yong Hong, Jan-Jan Wu, Yu-Ping Liu, Sheng-Yu Fu, Wei-Chung Hsu:
Processor-Tracing Guided Region Formation in Dynamic Binary Translation. ACM Trans. Archit. Code Optim. 15(4): 52:1-52:25 (2019) - [j6]Yu-Ping Liu, Ding-Yong Hong, Jan-Jan Wu, Sheng-Yu Fu, Wei-Chung Hsu:
Exploiting SIMD Asymmetry in ARM-to-x86 Dynamic Binary Translation. ACM Trans. Archit. Code Optim. 16(1): 2:1-2:24 (2019) - [c15]Chih-Min Lin, Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Exploiting Vector Processing in Dynamic Binary Translation. ICPP 2019: 93:1-93:10 - 2018
- [j5]Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Efficient and retargetable SIMD translation in a dynamic binary translator. Softw. Pract. Exp. 48(6): 1312-1330 (2018) - [j4]Ding-Yong Hong, Yu-Ping Liu, Sheng-Yu Fu, Jan-Jan Wu, Wei-Chung Hsu:
Improving SIMD Parallelism via Dynamic Binary Translation. ACM Trans. Embed. Comput. Syst. 17(3): 61:1-61:27 (2018) - [c14]Sheng-Yu Fu, Chih-Min Lin, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Exploiting SIMD capability in an ARMv7-to-ARMv8 dynamic binary translator. CASES 2018: 14:1-14:3 - [c13]Shih-Kai Lin, Ding-Yong Hong, Sheng-Yu Fu, Jan-Jan Wu, Wei-Chung Hsu:
Dynamic tuning of applications using restricted transactional memory. RACS 2018: 249-254 - 2017
- [c12]Yu-Ping Liu, Ding-Yong Hong, Jan-Jan Wu, Sheng-Yu Fu, Wei-Chung Hsu:
Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation. PACT 2017: 343-355 - [c11]Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Dynamic translation of structured Loads/Stores and register mapping for architectures with SIMD extensions. LCTES 2017: 31-40 - 2016
- [j3]Ding-Yong Hong, Chun-Chen Hsu, Cheng-Yi Chou, Wei-Chung Hsu, Pangfeng Liu, Jan-Jan Wu:
Optimizing Control Transfer and Memory Virtualization in Full System Emulators. ACM Trans. Archit. Code Optim. 12(4): 47:1-47:24 (2016) - [c10]Ding-Yong Hong, Sheng-Yu Fu, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Exploiting Longer SIMD Lanes in Dynamic Binary Translation. ICPADS 2016: 853-860 - 2015
- [j2]Chun-Chen Hsu, Ding-Yong Hong, Wei-Chung Hsu, Pangfeng Liu, Jan-Jan Wu:
A dynamic binary translation system in a client/server environment. J. Syst. Archit. 61(7): 307-319 (2015) - [c9]Sheng-Yu Fu, Ding-Yong Hong, Jan-Jan Wu, Pangfeng Liu, Wei-Chung Hsu:
SIMD Code Translation in an Enhanced HQEMU. ICPADS 2015: 507-514 - 2014
- [j1]Ding-Yong Hong, Jan-Jan Wu, Pen-Chung Yew, Wei-Chung Hsu, Chun-Chen Hsu, Pangfeng Liu, Chien-Min Wang, Yeh-Ching Chung:
Efficient and Retargetable Dynamic Binary Translation on Multicores. IEEE Trans. Parallel Distributed Syst. 25(3): 622-632 (2014) - [c8]Yi-Hong Lyu, Ding-Yong Hong, Tai-Yi Wu, Jan-Jan Wu, Wei-Chung Hsu, Pangfeng Liu, Pen-Chung Yew:
DBILL: an efficient and retargetable dynamic binary instrumentation framework using llvm backend. VEE 2014: 141-152 - 2013
- [c7]Chun-Chen Hsu, Pangfeng Liu, Jan-Jan Wu, Pen-Chung Yew, Ding-Yong Hong, Wei-Chung Hsu, Chien-Min Wang:
Improving dynamic binary optimization through early-exit guided code region formation. VEE 2013: 23-32 - 2012
- [c6]Ding-Yong Hong, Chun-Chen Hsu, Pen-Chung Yew, Jan-Jan Wu, Wei-Chung Hsu, Pangfeng Liu, Chien-Min Wang, Yeh-Ching Chung:
HQEMU: a multi-threaded and retargetable dynamic binary translator on multicores. CGO 2012: 104-113 - 2011
- [c5]Chun-Chen Hsu, Pangfeng Liu, Chien-Min Wang, Jan-Jan Wu, Ding-Yong Hong, Pen-Chung Yew, Wei-Chung Hsu:
LnQ: Building High Performance Dynamic Binary Translators with Existing Compiler Backends. ICPP 2011: 226-234 - 2010
- [c4]Ding-Yong Hong, Fang-Ping Pai, Shih-Hsiang Lo, Yeh-Ching Chung:
A Scalable HLA RTI System Based on Multiple-FedServ Architecture. UKSim 2010: 527-532
2000 – 2009
- 2009
- [c3]Shih-Hsiang Lo, Cheng-An Chiu, Fang-Ping Pai, Ding-Yong Hong, Yeh-Ching Chung:
MGRID: a modifiable-grid region matching approach for DDM in the HLA RTI. SpringSim 2009 - 2008
- [c2]Seetharami R. Seelam, I-Hsin Chung, Ding-Yong Hong, Hui-Fang Wen, Hao Yu:
Early experiences in application level I/O tracing on blue gene systems. IPDPS 2008: 1-8 - 2005
- [c1]Ding-Yong Hong, Ching-Wen You, Yeh-Ching Chung:
An Efficient MPI-IO for Noncontiguous Data Access over InfiniBand. ISPAN 2005: 140-147
Coauthor Index
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