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Yuan Wang 0001
Person information
- affiliation: Peking University, Institute of Microelectronics, Beijing, China
Other persons with the same name
- Yuan Wang — disambiguation page
- Yuan Wang 0002
— Tianjin University, State Key Laboratory of Precision Measurement Technology and Instrument, China
- Yuan Wang 0003
- Yuan Wang 0004
- Yuan Wang 0005 — Florida Atlantic University, Department of Mathematical Sciences, Boca Raton, FL, USA (and 1 more)
- Yuan Wang 0006
- Yuan Wang 0007 — Georgia Institute of Technology, Atlanta, GA, USA
- Yuan Wang 0008
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2020 – today
- 2024
- [j48]Shuo Feng
BrainQN: Enhancing the Robustness of Deep Reinforcement Learning with Spiking Neural Networks. Adv. Intell. Syst. 6(9) (2024) - [j47]Lindong Wu, Zongwei Wang, Lin Bao, Linbo Shan, Zhizhen Yu, Yunfan Yang, Shuangjie Zhang, Guandong Bai, Cuimei Wang, John Robertson, Yuan Wang, Yimao Cai, Ru Huang:
Investigation and mitigation of Mott neuronal oscillation fluctuation in spiking neural network. Sci. China Inf. Sci. 67(2) (2024) - [j46]Jiahao Song
A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM. IEEE J. Solid State Circuits 59(3): 842-854 (2024) - [j45]Kefei Liu
How the Brain Achieves Real-Time Vision: A Spiking Position Perception Model. IEEE Trans. Cogn. Dev. Syst. 16(3): 961-972 (2024) - [j44]Xin Qiao
A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 71(4): 1706-1718 (2024) - [j43]Qingyu Guo
CASCADE: A Framework for CNN Accelerator Synthesis With Concatenation and Refreshing Dataflow. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 5235-5248 (2024) - [j42]Qingyu Guo, Nanbing Pan, Xin Qiao
OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1899-1903 (2024) - [j41]Xin Qiao
An eDRAM-Based Computing-in-Memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2539-2543 (2024) - [j40]Chang Xue
A 768.7-2124.2 TOPS/W Time-Domain Computing-in-Memory Macro With Low Static Leakage and Precision-Configurable TDC. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2789-2793 (2024) - [j39]Kanglin Xiao
A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3263-3267 (2024) - [c68]Zilin Wang, Yi Zhong, Guang Chen, Shuo Feng, Youming Yang
A Hybrid Heterogeneous Neural Network Accelerator based on Systolic Array. AICAS 2024: 154-158 - [c67]Haikang Diao, Haoyang Luo, Jiahao Song, Bocheng Xu, Runsheng Wang, Yuan Wang, Xiyuan Tang:
A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI. CICC 2024: 1-2 - [c66]Xin Qiao, Jiahao Song, Youming Yang
MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks. CICC 2024: 1-2 - [c65]Zilong Shen, Jiaiun Tang, Haoyang Luo, Zhongyi Wu, Zongnan Wang, Xing Zhang, Xiyuan Tang, Yuan Wang:
A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation. CICC 2024: 1-2 - [c64]Zichen Kong
PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. DAC 2024: 47:1-47:6 - [c63]Tong Xie, Yixuan Hu, Renjie Wei, Meng Li, Yuan Wang, Runsheng Wang, Ru Huang:
ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer. DATE 2024: 1-6 - [c62]Zhenhui Dai, Jiawei Wang, Yi Zhong, Kunyu Feng, Cheng Zhao, Yuanyuan Jiang, Peiyu Chen
An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow. ISCAS 2024: 1-5 - [c61]Lindong Wu, Xuefei Lv, Shaoning Jin, Chaoyi Ban, Zongwei Wang, Yuan Wang, Yimao Cai:
A cascaded timestamp-free event camera image compression method for gesture recognition. ISIE 2024: 1-5 - [c60]Jiahao Song
30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing. ISSCC 2024: 490-492 - [i10]Tong Xie, Yixuan Hu, Renjie Wei, Meng Li, Yuan Wang, Runsheng Wang, Ru Huang:
ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer. CoRR abs/2402.12820 (2024) - [i9]Shuzhang Zhong, Ling Liang, Yuan Wang, Runsheng Wang, Ru Huang, Meng Li:
AdapMoE: Adaptive Sensitivity-based Expert Gating and Management for Efficient MoE Inference. CoRR abs/2408.10284 (2024) - 2023
- [j38]Chenglong Zou
Toward a Lossless Conversion for Spiking Neural Networks with Negative-Spike Dynamics. Adv. Intell. Syst. 5(12) (2023) - [j37]Jiahao Song
A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 1835-1845 (2023) - [j36]Kefei Liu
Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1590-1594 (2023) - [j35]Kanglin Xiao
A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 1816-1820 (2023) - [j34]Yi Zhong
An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4241-4245 (2023) - [c59]Yi Zhong, Zilin Wang, Xiaoxin Cui, Jian Cao, Yuan Wang:
Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation. AICAS 2023: 1-5 - [c58]Zilin Wang, Yi Zhong, Youming Yang
An Efficient Spiking Neural Network Accelerator with Sparse Weight. BioCAS 2023: 1-5 - [c57]Zilong Shen, Xiyuan Tang, Zhongyi Wu, Haoyang Luo, Zongnan Wang, Mingjie Liu, Xing Zhang, Yuan Wang:
A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization. CICC 2023: 1-2 - [c56]Jiahao Song
A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC. CICC 2023: 1-2 - [c55]Yixuan Hu, Tengyu Zhang, Meng Li, Renjie Wei, Liangzhen Lai, Yuan Wang, Runsheng Wang, Ru Huang:
Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network. DAC 2023: 1-6 - [c54]Yixuan Hu, Tengyu Zhang, Renjie Wei, Meng Li, Runsheng Wang, Yuan Wang, Ru Huang:
Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion. DATE 2023: 1-6 - [c53]Jinming Che, Jian Cao, Shuo Feng, Jue Chen, Yuan Wang:
Linear Leakage: Better Robustness for Spiking Neural Network. ICACT 2023: 417-423 - [c52]Yuan Zhang, Jian Cao, Jue Chen, Wenyu Sun, Yuan Wang:
Razor SNN: Efficient Spiking Neural Network with Temporal Embeddings. ICANN (5) 2023: 411-422 - [c51]Xiaochen Hao, Zijian Ding, Jieming Yin, Yuan Wang, Yun Liang:
Monad: Towards Cost-Effective Specialization for Chiplet-Based Spatial Accelerators. ICCAD 2023: 1-9 - [c50]Bingsen Wang, Jian Cao, Jue Chen, Shuo Feng, Yuan Wang:
A New ANN-SNN Conversion Method with High Accuracy, Low Latency and Good Robustness. IJCAI 2023: 3067-3075 - [c49]Zilin Wang, Yi Zhong, Xiaoxin Cui, Yisong Kuang, Yuan Wang:
A Spiking Neural Network Accelerator based on Ping-Pong Architecture with Sparse Spike and Weight. ISCAS 2023: 1-5 - [c48]Yifan He, Haikang Diao, Chen Tang, Wenbin Jia, Xiyuan Tang, Yuan Wang, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu:
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. ISSCC 2023: 130-131 - [c47]Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. ISSCC 2023: 176-177 - [i8]Xiaochen Hao, Zijian Ding, Jieming Yin, Yuan Wang, Yun Liang:
ALEGO: Towards Cost-Aware Architecture and Integration Co-Design for Chiplet-based Spatial Accelerators. CoRR abs/2302.11256 (2023) - [i7]Sebin Gracy, Yuan Wang, Philip E. Pare, César A. Uribe:
Multi-Competitive Virus Spread over a Time-Varying Networked SIS Model with an Infrastructure Network. CoRR abs/2303.08859 (2023) - [i6]Yuan Zhang, Jian Cao, Ling Zhang, Jue Chen, Wenyu Sun, Yuan Wang:
Razor SNN: Efficient Spiking Neural Network with Temporal Embeddings. CoRR abs/2306.17597 (2023) - 2022
- [j33]Kanglin Xiao
A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications. Microelectron. J. 126: 105506 (2022) - [j32]Chenglong Zou
Modular building blocks for mapping spiking neural networks onto a programmable neuromorphic processor. Microelectron. J. 129: 105612 (2022) - [j31]Zilong Shen
A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1547-1551 (2022) - [j30]Xin Qiao
A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2977-2981 (2022) - [j29]Yisong Kuang
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1631-1641 (2022) - [c46]Weichen Xu
Boosting Dense Long-Tailed Object Detection from Data-Centric View. ACCV (3) 2022: 558-574 - [c45]Kefei Liu, Xiaoxin Cui, Chenglong Zou
A Full-Neuron Memory Model Designed for Neuromorphic Systems. AICAS 2022: 138-141 - [c44]Xiuping Cui, Xiaochen Hao, Yun Liang, Guangyu Sun, Xiaoxin Cui, Yuan Wang, Ru Huang:
A Mapping Model of SNNs to Neuromorphic Hardware. AICAS 2022: 206-209 - [c43]Chenglong Zou
A Hybrid Spiking Recurrent Neural Network on Hardware for Efficient Emotion Recognition. AICAS 2022: 332-335 - [c42]Yuhao Yi, Yuan Wang, Xingkang He, Stacy Patterson, Karl Henrik Johansson:
A Sample-Based Algorithm for Approximately Testing r-Robustness of a Digraph. CDC 2022: 6478-6483 - [c41]Wenyu Sun, Jian Cao, Pengtao Xu, Xiangcheng Liu, Yuan Zhang, Yuan Wang:
An Once-for-All Budgeted Pruning Framework for ConvNets Considering Input Resolution. CVPR Workshops 2022: 2608-2617 - [c40]Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang:
A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations. ICTA 2022: 182-183 - [c39]Qingyu Guo, Xiaoxin Cui, Jian Zhang, Aifei Zhang, Xinjie Guo, Yuan Wang:
A 4-bit Integer-Only Neural Network Quantization Method Based on Shift Batch Normalization. ISCAS 2022: 707-711 - [c38]Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Nanbing Pan, Xin'an Wang, Yuan Wang:
A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation. ISCAS 2022: 2551-2555 - [c37]Nanbing Pan, Xiaoxin Cui, Xin Qiao, Kanglin Xiao, Qingyu Guo, Yuan Wang:
A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro. ISCAS 2022: 2561-2565 - [c36]Yisong Kuang, Xiaoxin Cui, Chenglong Zou
An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight. ISCAS 2022: 3468-3472 - [c35]Zilong Shen, Yize Wang, Xing Zhang, Yuan Wang:
A Novel Low-Leakage ESD Power Clamp Circuit with Adjustable Transient Response Time. ISCAS 2022: 3488-3492 - [i5]Yuhao Yi, Yuan Wang, Xingkang He, Stacy Patterson, Karl Henrik Johansson:
A Sample-Based Algorithm for Approximately Testing r-Robustness of a Digraph. CoRR abs/2207.12110 (2022) - [i4]Yuan Wang, Sebin Gracy, César A. Uribe, Hideaki Ishii, Karl Henrik Johansson:
A State Feedback Controller for Mitigation of Continuous-Time Networked SIS Epidemics. CoRR abs/2210.04169 (2022) - 2021
- [j28]Jiahao Song
TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3377-3387 (2021) - [j27]Yisong Kuang
A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2655-2659 (2021) - [c34]Jiahao Song
A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing. A-SSCC 2021: 1-3 - [c33]Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou
A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. ISCAS 2021: 1-5 - [c32]Yi Zhong, Xiaoxin Cui, Yisong Kuang, Kefei Liu, Yuan Wang, Ru Huang:
A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS. ISCAS 2021: 1-5 - [i3]Yuan Wang, Sebin Gracy, Hideaki Ishii, Karl Henrik Johansson:
Suppressing the endemic equilibrium in SIS epidemics: A state dependent approach. CoRR abs/2106.00122 (2021) - [i2]Qingyu Guo, Yuan Wang, Xiaoxin Cui:
Integer-Only Neural Network Quantization Scheme Based on Shift-Batch-Normalization. CoRR abs/2106.00127 (2021) - 2020
- [j26]Yize Wang
A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics. IEEE Access 8: 64730-64738 (2020) - [j25]Yawen Zhang
Parallel Hybrid Stochastic-Binary-Based Neural Network Accelerators. IEEE Trans. Circuits Syst. 67-II(12): 3387-3391 (2020) - [c31]Yawen Zhang, Sheng Lin, Runsheng Wang, Yanzhi Wang, Yuan Wang, Weikang Qian, Ru Huang:
When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing. DATE 2020: 1287-1290 - [c30]Yawen Zhang, Runsheng Wang, Yixuan Hu, Weikang Qian, Yanzhi Wang, Yuan Wang, Ru Huang:
Accurate and Energy-Efficient Implementation of Non-Linear Adder in Parallel Stochastic Computing using Sorting Network. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j24]Lizhong Zhang, Yuan Wang, Yize Wang, Xing Zhang, Yandong He:
Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection. Sci. China Inf. Sci. 62(6): 62402:1-62402:8 (2019) - [c29]Xinyue Zhang, Jiahao Song, Yuan Wang, Yawen Zhang, Zuodong Zhang, Runsheng Wang, Ru Huang:
An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. ASICON 2019: 1-4 - [c28]Zhao Zhao, Yuan Wang, Xinyue Zhang, Xiaoxin Cui, Ru Huang:
An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training. BioCAS 2019: 1-4 - [c27]Xinyue Zhang, Yuan Wang, Yawen Zhang, Jiahao Song, Zuodong Zhang, Kaili Cheng, Runsheng Wang, Ru Huang:
Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. ICICDT 2019: 1-4 - [c26]Zhao Zhao, Yuan Wang, Cheng Li, Xiaoxin Cui, Ru Huang:
A Sparse Event-Driven Unsupervised Learning Network with Adaptive Exponential Integrate-and-Fire Model. ICICDT 2019: 1-4 - [c25]Weikang Qian, Runsheng Wang, Yuan Wang, Marc D. Riedel
A Survey of Computation-Driven Data Encoding. SiPS 2019: 7-12 - [c24]Yawen Zhang, Xinyue Zhang, Jiahao Song, Yuan Wang, Ru Huang, Runsheng Wang:
Parallel Convolutional Neural Network (CNN) Accelerators Based on Stochastic Computing. SiPS 2019: 19-24 - [i1]Yawen Zhang, Runsheng Wang, Xinyue Zhang, Zherui Zhang, Jiahao Song, Zuodong Zhang, Yuan Wang, Ru Huang:
A Parallel Bitstream Generator for Stochastic Computing. CoRR abs/1904.09554 (2019) - 2018
- [j23]Yuan Wang
A 1-Gbps reference-less burst-mode CDR with embedded TDC in a 65-nm CMOS process. Int. J. Circuit Theory Appl. 46(8): 1565-1576 (2018) - [c23]Cheng Li, Yuan Wang, Jin Zhang, Xiaoxin Cui, Ru Huang:
A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition. BioCAS 2018: 1-4 - [c22]Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang:
Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. ISCAS 2018: 1-5 - [c21]Lu Zhang, Jin Zhang, Yuan Wang, Xing Zhang, Ru Huang:
A Multi-Mode Silicon Neuron Circuit With High Robustness Against PVT Variation. ISCAS 2018: 1-4 - 2017
- [j22]Yize Wang, Yuan Wang
A novel TLP-based method to deliver IEC 61000-4-2 ESD stress. IEICE Electron. Express 14(9): 20170163 (2017) - [j21]Yuan Wang
Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness. IEICE Trans. Electron. 100-C(3): 344-347 (2017) - [j20]Yuan Wang
Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process. Int. J. Circuit Theory Appl. 45(6): 851-858 (2017) - [c20]Yukuai Chen, Jian Cao, Zhang Qihui, Yuan Wang
A novel equivalent circuit model of the surge wave generator. ASICON 2017: 807-810 - [c19]Guangyi Lu, Yuan Wang
Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process. ISCAS 2017: 1-4 - [c18]Yunfan Yang, Song Jia, Yuan Wang
A reliable true random number generator based on novel chaotic ring oscillator. ISCAS 2017: 1-4 - [c17]Jin Zhang, Yuan Wang
Compact digital-controlled neuromorphic circuit with low power consumption. ISCAS 2017: 1-4 - 2016
- [j19]Yuan Wang
Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. Sci. China Inf. Sci. 59(4): 042407:1-042407:9 (2016) - [j18]Jian Cao, Jingya Xu, Yuan Wang
A compact SCR model using advanced BJT models and standard SPICE elements. Sci. China Inf. Sci. 59(10): 109302 (2016) - [j17]Guangyi Lu, Yuan Wang
Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process. Sci. China Inf. Sci. 59(12): 122401:1-122401:9 (2016) - [j16]Jian Cao, Yize Wang, Yuan Wang
A novel SPICE circuit model of electrostatic discharge (ESD) generator. IEICE Electron. Express 13(9): 20160238 (2016) - [j15]Guangyi Lu, Yuan Wang
Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process. IEICE Trans. Electron. 99-C(5): 590-596 (2016) - [j14]Wenyi Tang, Song Jia, Yuan Wang
A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis. IEICE Trans. Electron. 99-C(8): 956-962 (2016) - [j13]Yuan Wang
A 4.8-6.8 GHz low phase noise LC VCO in 0.13-µm CMOS technology. Int. J. Circuit Theory Appl. 44(9): 1758-1764 (2016) - [j12]Song Jia, Ziyi Wang, Shilin Yan, Yuan Wang
A true single-phase clock dual-modulus prescaler with enhanced robustness against leakage currents. Int. J. Circuit Theory Appl. 44(10): 1895-1900 (2016) - [c16]Yuan Wang
Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics. ISCAS 2016: 1-4 - [c15]Guangyi Lu, Yuan Wang
A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications. ISCAS 2016: 265-268 - [c14]Song Jia, Ziyi Wang, Zijin Li, Yuan Wang
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic. ISCAS 2016: 2751-2754 - 2015
- [j11]Guangyi Lu, Yuan Wang
Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. Sci. China Inf. Sci. 58(4): 1-9 (2015) - [j10]Yuan Wang
Novel DEM Technique for Current-Steering DAC in 65-nm CMOS Technology. IEICE Trans. Electron. 98-C(12): 1193-1195 (2015) - [c13]Jian Cao, Zhenxu Ye, Yuan Wang
A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network. ASICON 2015: 1-4 - [c12]Jiyu Chen, Song Jia, Yuan Wang:
A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier. ASICON 2015: 1-4 - [c11]Fangyuan Dang, Yuan Wang
Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation. ASICON 2015: 1-4 - [c10]Nan Han, Yuan Wang
Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection. ASICON 2015: 1-4 - [c9]Song Jia, Weiting Li, Wenyi Tang, Yuan Wang
A low power and high speed CAM design using pulsed voltage for search-line. ASICON 2015: 1-4 - [c8]Mengyin Jiang, Yuan Wang
A reference-less all-digital burst-mode CDR with embedded TDC. ASICON 2015: 1-4 - [c7]Song Jia, Shilin Yan, Yuan Wang
A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic. ISCAS 2015: 890-893 - [c6]Yuequan Liu, Yuan Wang
180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance. ISCAS 2015: 1394-1397 - 2014
- [j9]Peng Zhang, Yuan Wang
Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp. Sci. China Inf. Sci. 57(2): 1-6 (2014) - 2013
- [j8]Yuan Wang
Thermo data-weighted average dynamic element matching (DEM) encoder for current-steering DACs. IEICE Electron. Express 10(20): 20130459 (2013) - [j7]Song Jia, Li Liu, Xiayu Li, Fengfeng Wu, Yuan Wang
Data Convertors Design for Optimization of the DDPL Family. IEICE Trans. Electron. 96-C(9): 1195-1200 (2013) - [j6]Song Jia, Heqing Xu, Fengfeng Wu, Yuan Wang:
A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs. IEICE Trans. Electron. 96-C(9): 1205-1207 (2013) - [j5]Fengfeng Wu, Song Jia, Qinglong Meng, Shigong Lv, Yuan Wang
Improved CRC Calculation Strategies for 64-bit Serial RapidIO. IEICE Trans. Electron. 96-C(10): 1330-1338 (2013) - [c5]Baoguang Liu, Yuan Wang
A novel dynamic element match technique in current-steering DAC. ASICON 2013: 1-4 - [c4]Guangyi Lu, Yuan Wang
Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. ASICON 2013: 1-4 - [c3]Heqing Xu, Song Jia, Jiyu Chen, Yuan Wang
A current mode sense amplifier with self-compensation circuit for SRAM application. ASICON 2013: 1-4 - 2012
- [j4]Xiayu Li, Song Jia, Limin Liu, Yuan Wang
Design of novel, semi-transparent flip-flops (STFF) for high speed and low power application. Sci. China Inf. Sci. 55(10): 2390-2398 (2012) - [j3]Xiayu Li, Song Jia, Limin Liu, Yuan Wang
A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF). IEICE Trans. Electron. 95-C(6): 1125-1127 (2012) - 2011
- [j2]Hongyi Li, Yuan Wang
Novel single-loop multi-bit sigma-delta modulator using OTA sharing technique without DEM. IEICE Electron. Express 8(24): 2041-2047 (2011) - [c2]Peng Zhang, Yuan Wang
A novel multi-finger layout strategy for GGnMOS ESD protection device. ASICON 2011: 275-278 - 2010
- [j1]Fengfeng Wu, Song Jia, Yuan Wang
Low swing drivers based on charge redistribution. Sci. China Inf. Sci. 53(11): 2377-2388 (2010)
2000 – 2009
- 2007
- [c1]Liangguo Shen, Zushu Yan, Xing Zhang, Yuanfu Zhao, Yuan Wang:
Design of High-Performance Voltage Regulators Based on Frequency-Dependent Feedback Factor. ISCAS 2007: 3828-3831
Coauthor Index
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last updated on 2024-12-13 19:13 CET by the dblp team
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