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Yasuhiro Ogasahara
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2020 – today
- 2020
- [j11]Yasuhiro Ogasahara
, Yohei Hori
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping. Integr. 71: 144-153 (2020)
2010 – 2019
- 2017
- [c11]Toshihiro Katashita, Yohei Hori
Prototype of USB stick-sized PUF module for authentication and key generation. GCCE 2017: 1-2 - 2016
- [c10]Yasuhiro Ogasahara, Yohei Hori
Implementation of pseudo linear feedback shift register physical unclonable function on silicon. ISCAS 2016: 758-761 - 2015
- [j10]Yasuhiro Ogasahara
Impacts of flexible Vth control, low process variability, and steep SS with low on-current of new structure transistors to ultra-low voltage designs. IEICE Electron. Express 12(15): 20150460 (2015) - [j9]Toshitsugu Sakamoto, Yukihide Tsuji
A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM. IEEE Micro 35(6): 13-23 (2015) - [c9]Toshitsugu Sakamoto, Yukihide Tsuji
0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM. COOL Chips 2015: 1-3 - [c8]Yasuhiro Ogasahara, Yohei Hori
Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness tests. GCCE 2015: 550-551 - 2014
- [j8]Toshiki Kanamoto
Resistivity-based modeling of substrate non-uniformity for low-resistivity substrate. IEICE Electron. Express 11(3): 20130813 (2014) - 2013
- [j7]Yasuhiro Ogasahara
Supply Noise Suppression by Triple-Well Structure. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 781-785 (2013)
2000 – 2009
- 2009
- [j6]Yasuhiro Ogasahara
All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform. IEEE J. Solid State Circuits 44(6): 1745-1755 (2009) - 2008
- [j5]Toshiki Kanamoto
Impact of Well Edge Proximity Effect on Timing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3461-3464 (2008) - [j4]Yasuhiro Ogasahara
Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects. IEEE J. Solid State Circuits 43(3): 718-728 (2008) - [c7]Yasuhiro Ogasahara, Masanori Hashimoto
Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification. ASP-DAC 2008: 107-108 - 2007
- [j3]Yasuhiro Ogasahara
Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 724-731 (2007) - [j2]Yasuhiro Ogasahara
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement. IEEE Trans. Circuits Syst. II Express Briefs 54-II(10): 868-872 (2007) - [c6]Yasuhiro Ogasahara
Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect. CICC 2007: 783-786 - [c5]Toshiki Kanamoto
Impact of well edge proximity effect on timing. ESSCIRC 2007: 115-118 - 2006
- [j1]Masanao Ise, Yasuhiro Ogasahara
W-CDMA Channel Codec by Configurable Processors. Intell. Autom. Soft Comput. 12(3): 317-329 (2006) - [c4]Yasuhiro Ogasahara
Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects. CICC 2006: 721-724 - [c3]Yasuhiro Ogasahara
Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation. CICC 2006: 861-864 - [c2]Yasuhiro Ogasahara, Masanori Hashimoto
Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. ICCD 2006: 70-75 - 2005
- [c1]Yasuhiro Ogasahara, Masanori Hashimoto
Measurement and analysis of delay variation due to inductive coupling. CICC 2005: 305-308
Coauthor Index
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