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Chien-Ching Lin
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2010 – 2019
- 2010
- [j7]Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee:
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. IEEE J. Solid State Circuits 45(2): 422-432 (2010)
2000 – 2009
- 2009
- [j6]Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. IEEE Trans. Circuits Syst. II Express Briefs 56-II(9): 734-738 (2009) - [j5]Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen-Yi Lee:
A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 1960-1967 (2009) - 2008
- [c8]Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua:
Multi-mode message passing switch networks applied for QC-LDPC decoder. ISCAS 2008: 752-755 - 2007
- [j4]Terng-Ren Hsu, Chien-Ching Lin, Terng-Yin Hsu, Chen-Yi Lee:
MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 879-884 (2007) - [j3]Yen-Chin Liao, Chien-Ching Lin, Hsie-Chia Chang, Chih-Wei Liu:
Self-Compensation Technique for Simplified Belief-Propagation Algorithm. IEEE Trans. Signal Process. 55(6-2): 3061-3072 (2007) - [c7]Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su:
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. CICC 2007: 273-276 - 2006
- [j2]Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee:
A low power turbo/Viterbi decoder for 3GPP2 applications. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 426-430 (2006) - [c6]Lei-Fone Chen, Yuan Chen, Lu-Chung Chien, Ying-Hao Ma, Chia-Hao Lee, Yu-Wei Lin, Chien-Ching Lin, Hsuan-Yu Liu, Terng-Yin Hsu, Chen-Yi Lee:
A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications. ISSCC 2006: 1002-1011 - 2005
- [j1]Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee:
Design of a power-reduction Viterbi decoder for WLAN applications. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(6): 1148-1156 (2005) - [c5]Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 3.33Gb/s (1200,720) low-density parity check code decoder. ESSCIRC 2005: 211-214 - 2004
- [c4]Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee:
A dual mode channel decoder for 3GPP2 mobile wireless communications. ESSCIRC 2004: 483-486 - [c3]Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee:
A power and area efficient multi-mode FEC processor. ISCAS (2) 2004: 253-256 - [c2]Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang:
Multi-level memory systems using error control codes. ISCAS (2) 2004: 393-396 - 2003
- [c1]Chien-Ching Lin, Chia-Cho Wu, Chen-Yi Lee:
A low power and high speed Viterbi decoder chip for WLAN applications. ESSCIRC 2003: 723-726
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