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Hideki Ando
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2020 – today
- 2024
- [c18]Kenichiro Mori, Sota Kosugi, Hiroto Yoshida, Hajime Shimada, Hideki Ando:
Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue Queue. MICRO 2024: 493-506 - 2022
- [j16]Yasutaka Matsuda, Ryota Shioya, Hideki Ando:
Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison. IEICE Trans. Inf. Syst. 105-D(2): 320-332 (2022) - [c17]Hideki Ando:
Segmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and Area. ICCD 2022: 360-363
2010 – 2019
- 2019
- [j15]Reoma Matsuo
, Ryota Shioya, Hideki Ando
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline. IEEE Comput. Archit. Lett. 18(2): 170-173 (2019) - [c16]Hideki Ando:
SWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular Queue. MICRO 2019: 506-518 - 2018
- [j14]Keita Doi, Ryota Shioya, Hideki Ando:
Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications. J. Inf. Process. 26: 445-460 (2018) - [c15]Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando:
A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode. ARCS 2018: 211-224 - [c14]Shinji Sakai, Taishi Suenaga, Ryota Shioya, Hideki Ando:
Rearranging Random Issue Queue with High IPC and Short Delay. ICCD 2018: 123-131 - [c13]Hideki Ando:
Performance Improvement by Prioritizing the Issue of the Instructions in Unconfident Branch Slices. MICRO 2018: 82-94 - 2016
- [j13]Hideki Ando, Ryota Shioya:
Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control. IEICE Trans. Inf. Syst. 99-D(2): 341-350 (2016) - [j12]Ryota Shioya, Hideki Ando:
Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency. IEICE Trans. Inf. Syst. 99-D(3): 630-640 (2016) - [j11]Ryota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando:
FXA: Executing Instructions in Front-End for Energy Efficiency. IEICE Trans. Inf. Syst. 99-D(4): 1092-1107 (2016) - 2014
- [j10]Yuya Kora, Kyohei Yamaguchi, Hideki Ando:
MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism. IEICE Trans. Inf. Syst. 97-D(12): 3110-3123 (2014) - [c12]Ryota Shioya, Hideki Ando:
Energy efficiency improvement of renamed trace cache through the reduction of dependent path length. ICCD 2014: 416-423 - [c11]Ryota Shioya, Masahiro Goshima, Hideki Ando:
A Front-End Execution Architecture for High Energy Efficiency. MICRO 2014: 419-431 - 2013
- [c10]Yuya Kora, Kyohei Yamaguchi, Hideki Ando:
MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP. MICRO 2013: 37-48 - 2012
- [j9]Kyohei Yamaguchi, Yuya Kora, Hideki Ando:
Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification. IEICE Trans. Inf. Syst. 95-D(9): 2235-2246 (2012) - 2011
- [c9]Kyohei Yamaguchi, Yuya Kora, Hideki Ando:
Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path. ICCD 2011: 313-319 - 2010
- [j8]Yusuke Tanaka, Hideki Ando:
Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction. IEICE Trans. Inf. Syst. 93-D(12): 3294-3305 (2010)
2000 – 2009
- 2009
- [j7]Kazunaga Hyodo, Kengo Iwamoto, Hideki Ando:
Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation. IEICE Trans. Inf. Syst. 92-D(11): 2186-2195 (2009) - [c8]Yusuke Tanaka, Hideki Ando:
Reducing register file size through instruction pre-execution enhanced by value prediction. ICCD 2009: 238-245 - 2008
- [j6]Akihiro Yamamoto, Yusuke Tanaka, Hideki Ando, Toshio Shimada:
Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation. Inf. Media Technol. 3(4): 755-767 (2008) - 2007
- [c7]Akihiro Yamamoto, Yusuke Tanaka, Hideki Ando, Toshio Shimada:
Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation. MEDEA@PACT 2007: 33-40 - 2006
- [j5]Akio Nakajima, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada:
Limits of Thread-Level Parallelism in Non-numerical Programs. Inf. Media Technol. 1(2): 851-859 (2006) - 2003
- [c6]Hajime Shimada, Hideki Ando, Toshio Shimada:
Pipeline stage unification: a low-energy consumption technique for future mobile processors. ISLPED 2003: 326-329 - 2002
- [c5]Ryo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada:
A preactivating mechanism for a VT-CMOS cache using address prediction. ISLPED 2002: 247-250
1990 – 1999
- 1999
- [j4]Hideki Ando, Yoshinobu Oasa, Ichiro Suzuki, Masafumi Yamashita:
Distributed memoryless point convergence algorithm for mobile robots with limited visibility. IEEE Trans. Robotics Autom. 15(5): 818-828 (1999) - [c4]Ryotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata:
An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. EUROMICRO 1999: 1432-1440 - 1998
- [j3]Chikako Nakanishi, Hideki Ando, Tetsuya Hara, Masao Nakaya:
Software pipelining with path selection. Syst. Comput. Jpn. 29(9): 74-86 (1998) - 1996
- [c3]Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya:
Performance Comparison of ILP Machines with Cycle Time Evaluation. ISCA 1996: 213-224 - 1995
- [j2]Chikako Nakanishi, Hideki Ando, Hirohisa Machida, Masao Nakaya:
Code scheduling on a superscalar processor: SARCH. Syst. Comput. Jpn. 26(9): 13-22 (1995) - [c2]Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya:
Unconstrained Speculative Execution with Predicated State Buffering. ISCA 1995: 126-137 - 1993
- [c1]Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya:
Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. ICCD 1993: 106-113
1980 – 1989
- 1988
- [j1]Hideki Ando, Masao Nakaya, Hiroki Hona, Ihuo Iizuka, Yasutaka Horiba:
A DSP line equalizer VLSI for TCM digital subscriber-line transmission. IEEE J. Solid State Circuits 23(1): 118-123 (1988)
Coauthor Index
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