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Tomohiro Yoneda
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2020 – today
- 2023
- [c55]Yuji Yamada, Nesrine Berjab, Tomohiro Yoneda, Kenji Kise:
A remote partial-reconfigurable SoC with a RISC-V soft processor targeting low-end FPGAs. MCSoC 2023: 31-37 - 2020
- [c54]Tomohiro Yoneda, Masashi Imai:
Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices. ASYNC 2020: 102-110
2010 – 2019
- 2019
- [c53]Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto
, Atsushi Kurokawa, Masashi Imai:
Hardware Trojan Insertion and Detection in Asynchronous Circuits. ASYNC 2019: 134-143 - [i2]Tomohiro Yoneda, Peter A. Beerel, Alex Yakovlev, Masashi Imai:
Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133). NII Shonan Meet. Rep. 2019 (2019) - 2018
- [j28]Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
MTJ-based asynchronous circuits for Re-initialization free computing against power failures. Microelectron. J. 82: 46-61 (2018) - [c52]Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda:
Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols. ASYNC 2018: 1-8 - 2017
- [j27]Hiroshi Saito, Masashi Imai, Tomohiro Yoneda:
Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1363-1373 (2017) - [c51]Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda:
MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC 2017: 118-125 - [c50]Hai-Phong Phan, Xuan-Tu Tran
Power consumption estimation using VNOC2.0 simulator for a fuzzy-logic based low power Network-on-Chip. ICICDT 2017: 1-4 - 2016
- [j26]Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers
An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis. Sci. Comput. Program. 118: 24-39 (2016) - [c49]Hiroshi Saito, Masashi Imai, Tomohiro Yoneda:
A task allocation method for the DTTR scheme based on task scheduling of fault patterns. ISCAS 2016: 237-240 - [c48]Sarat Yoowattana, Tomohiro Yoneda:
Improvement of Line Coding Overhead Targeting Both Run-Length and DC-Balance. MCSoC 2016: 15-22 - [c47]Hiroshi Saito, Masashi Imai, Tomohiro Yoneda:
A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks. MCSoC 2016: 169-176 - [c46]Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda:
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. NOCS 2016: 1-8 - 2015
- [j25]Masashi Imai, Tomohiro Yoneda:
Novel Implementation Method of Multiple-Way Asynchronous Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1519-1528 (2015) - [c45]Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Kenji Kise:
Dependable real-time task execution scheme for a many-core platform. DFTS 2015: 197-204 - [c44]Tomohiro Yoneda, Masashi Imai:
A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits. ICCD 2015: 395-398 - 2014
- [j24]Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. 97-D(6): 1546-1556 (2014) - [c43]Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura:
An NoC-based evaluation platform for safety-critical automotive applications. APCCAS 2014: 679-682 - [c42]Masashi Imai, Tomohiro Yoneda:
Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits. APCCAS 2014: 687-690 - [c41]Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers
Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip. FMICS 2014: 48-62 - [c40]Masashi Imai, Tomohiro Yoneda:
Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. ISCAS 2014: 141-144 - 2013
- [j23]Masashi Imai, Tomohiro Yoneda:
Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories. IEICE Trans. Inf. Syst. 96-D(9): 1914-1925 (2013) - [i1]Tomohiro Yoneda, José Flich Cardo, Jiang Xu, Michihiro Koibuchi:
Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8). NII Shonan Meet. Rep. 2013 (2013) - 2012
- [c39]Tomohiro Yoneda, Masashi Imai:
Dependable routing in multi-chip NoC platforms for automotive applications. DFT 2012: 217-224 - [c38]Hiroshi Saito, Tomohiro Yoneda, Yuichi Nakamura:
An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip. MCSoC 2012: 100-106 - [c37]Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Multi-chip NoCs for Automotive Applications. PRDC 2012: 105-110 - [c36]Masashi Imai, Tomohiro Yoneda:
Performance Modeling and Analysis of On-chip Networks for Real-Time Applications. PRDC 2012: 111-120 - 2011
- [j22]Scott Little, David Walter
Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 617-630 (2011) - [c35]Masashi Imai, Tomohiro Yoneda:
Improving Dependability and Performance of Fully Asynchronous On-chip Networks. ASYNC 2011: 65-76 - [c34]Masashi Imai, Tomohiro Yoneda:
Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories. DFT 2011: 463-471 - [c33]Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano:
A Dynamic Link-Width Optimization for Network-on-Chip. RTCSA (2) 2011: 106-108 - [e2]Leon Alkalai, Timothy Tsai, Tomohiro Yoneda:
17th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2011, Pasadena, CA, USA, December 12-14, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-2005-5 [contents] - 2010
- [j21]Chammika Mannakkara, Tomohiro Yoneda:
Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol. IEICE Trans. Inf. Syst. 93-D(8): 2145-2161 (2010) - [j20]Kedar S. Namjoshi, Tomohiro Yoneda:
Preface. Int. J. Found. Comput. Sci. 21(2) (2010) - [j19]Hao Zheng, Haiqiong Yao, Tomohiro Yoneda:
Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement. IEEE Trans. Computers 59(4): 561-573 (2010) - [c32]Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, Takashi Nanya:
A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. ISCAS 2010: 925-928
2000 – 2009
- 2009
- [j18]Naohiro Hamada, Yuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya:
A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation. Inf. Media Technol. 4(2): 211-226 (2009) - [j17]Naohiro Hamada, Yuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers
A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation. IPSJ Trans. Syst. LSI Des. Methodol. 2: 64-79 (2009) - [c31]Masashi Imai, Tomohiro Yoneda, Takashi Nanya:
N-way ring and square arbiters. ICCD 2009: 125-130 - [c30]Hao Zheng, Haiqiong Yao, Tomohiro Yoneda:
Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs. ISVLSI 2009: 175-180 - 2008
- [j16]Frédéric Béal, Tomohiro Yoneda, Chris J. Myers:
Hazard Checking of Timed Asynchronous Circuits Revisited. Fundam. Informaticae 88(4): 411-435 (2008) - [j15]Frédéric Béal, Tomohiro Yoneda, Chris J. Myers
A Conservative Framework for Safety-Failure Checking. IEICE Trans. Inf. Syst. 91-D(3): 642-654 (2008) - [j14]David Walter
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2223-2235 (2008) - [c29]Naohiro Hamada, Yuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers
A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). ACSD 2008: 50-55 - [c28]Chammika Mannakkara, Tomohiro Yoneda:
Asynchronous pipeline controller based on early acknowledgement protocol. ACSD 2008: 118-127 - 2007
- [j13]Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers
Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2790-2799 (2007) - [j12]Curtis A. Nelson, Chris J. Myers
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 592-605 (2007) - [j11]Tomohiro Yoneda, Chris J. Myers
Synthesis of Timed Circuits Based on Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1177-1195 (2007) - [c27]Frédéric Béal, Tomohiro Yoneda, Chris J. Myers
Hazard Checking of Timed Asynchronous Circuits Revisited. ACSD 2007: 51-60 - [c26]David Walter
Symbolic Model Checking of Analog/Mixed-Signal Circuits. ASP-DAC 2007: 316-323 - [e1]Kedar S. Namjoshi, Tomohiro Yoneda, Teruo Higashino, Yoshio Okamura:
Automated Technology for Verification and Analysis, 5th International Symposium, ATVA 2007, Tokyo, Japan, October 22-25, 2007, Proceedings. Lecture Notes in Computer Science 4762, Springer 2007, ISBN 978-3-540-75595-1 [contents] - 2006
- [j10]Hao Zheng, Chris J. Myers
Verification of timed circuits with failure-directed abstractions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 403-412 (2006) - [c25]Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers
ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. CIT 2006: 172 - [c24]Tomohiro Yoneda, Chris J. Myers:
Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. ATVA 2006: 229-244 - [c23]Scott Little, Nicholas Seegmiller, David Walter
Verification of analog/mixed-signal circuits using labeled hybrid petri nets. ICCAD 2006: 275-282 - 2005
- [j9]Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. IEICE Trans. Inf. Syst. 88-D(7): 1646-1661 (2005) - [j8]Tomoya Kitai, Tomohiro Yoneda, Chris J. Myers
Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation. IEICE Trans. Inf. Syst. 88-D(11): 2555-2564 (2005) - [c22]Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers
High Level Synthesis of Timed Asynchronous Circuits. ASYNC 2005: 178-189 - 2004
- [c21]Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers:
Synthesis of Speed Independent Circuits Based on Decomposition. ASYNC 2004: 135-145 - [c20]Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers:
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. ATVA 2004: 339-353 - [c19]Scott Little, David Walter
Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. ATVA 2004: 426-440 - 2003
- [c18]Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda:
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. ICCAD 2003: 424-432 - [c17]Hao Zheng, Chris J. Myers, David Walter
Verification of Timed Circuits with Failure Directed Abstractions. ICCD 2003: 28-35 - 2002
- [j7]Tomohiro Yoneda, Eric Mercer, Chris Myers:
Modular Synthesis of Timed Circuits Using Partial Order Reduction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2684-2692 (2002) - [c16]Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers:
Automatic Derivation of Timing Constraints by Failure Analysis. CAV 2002: 195-208 - [c15]Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers
Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. PRDC 2002: 210-220 - [c14]Eric Mercer, Chris J. Myers
Modular Synthesis of Timed Circuits using Partial Order Reduction. Theory and Practice of Timed Systems @ ETAPS 2002: 180-201 - 2001
- [j6]Koichi Masukura, Minoru Tomisaka, Tomohiro Yoneda:
Verification of asynchronous circuits based on zero-suppressed BDDs. Syst. Comput. Jpn. 32(2): 43-54 (2001) - [j5]Hiroshi Toshima, Tomohiro Yoneda:
Efficient verification by exploiting symmetry and abstraction. Syst. Comput. Jpn. 32(14): 41-53 (2001) - [c13]Bin Zhou, Tomohiro Yoneda, Bernd-Holger Schlingloff
Conformance and mirroring for timed asychronous circuits. ASP-DAC 2001: 341-346 - [c12]Bin Zhou, Tomohiro Yoneda, Chris J. Myers:
Framework of Timed Trace Theoretic Verification Revisited. Asian Test Symposium 2001: 437-442 - [c11]Tomoya Kitai, Tomohiro Yoneda:
Partial Order Reduction in Verification of Wheel Structured Parameterized Circuits. PRDC 2001: 173-182 - 2000
- [c10]Tomohiro Yoneda:
VINAS-P: A Tool for Trace Theoretic Verification of Timed Asynchronous Circuits. CAV 2000: 572-575
1990 – 1999
- 1999
- [c9]Tomohiro Yoneda, Hiroshi Ryu:
Timed Trace Theoretic Verification Using Partial Order Reduction. ASYNC 1999: 108- - [c8]Märt Saarepera, Tomohiro Yoneda:
A Self-Timed Implementation of Boolean Functions. ASYNC 1999: 243- - [c7]Tomohiro Yoneda:
Verification of Abstracted Instruction Cache of TITAC2: A Case Study. VLSI 1999: 373-384 - 1998
- [c6]Tomohiro Yoneda, Yutaka Ohtsuka, Märt Saarepera:
Verification of Parameterized Asynchronous Circuits: A Case Study. ACSD 1998: 64-74 - [c5]Tomohiro Yoneda, Bin Zhou, Bernd-Holger Schlingloff
Verification of Bounded Delay Asynchronous Circuits with Timed Traces. AMAST 1998: 59-73 - 1997
- [j4]Tomohiro Yoneda, Bernd-Holger Schlingloff
Efficient Verification of Parallel Real-Time Systems. Formal Methods Syst. Des. 11(2): 187-215 (1997) - [j3]Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya:
Verification of asynchronous logic circuit design using process algebra. Syst. Comput. Jpn. 28(8-9): 33-43 (1997) - 1996
- [c4]Tomohiro Yoneda, Takashi Yoshikawa:
Using partial orders for trace theoretic verification of asynchronous circuits. ASYNC 1996: 152-163 - [c3]Tomohiro Yoneda, Hideyuki Hatori, Atsushi Takahara, Shin-ichi Minato:
BDDs vs. Zero-Suppressed BDDs: for CTL Symbolic Model Checking of Petri Nets. FMCAD 1996: 435-449 - 1993
- [c2]Tomohiro Yoneda, Atsufumi Shibayama, Bernd-Holger Schlingloff
Efficient Verification of Parallel Real-Time Systems. CAV 1993: 321-346 - 1991
- [j2]Tomohiro Yoneda, Yoshihiro Tohma, Yutaka Kondo:
Acceleration of timing verification method based on time petri nets. Syst. Comput. Jpn. 22(12): 37-52 (1991)
1980 – 1989
- 1989
- [c1]Tomohiro Yoneda, Kazutoshi Nakade, Yoshihiro Tohma:
A fast timing verification method based on the independence of units. FTCS 1989: 134-141 - 1985
- [j1]Tomohiro Yoneda, Takashi Suzuoka, Yoshihiro Tohma:
Interrupt handling in the loosely synchronized TMR system. Syst. Comput. Jpn. 16(5): 50-59 (1985)
Coauthor Index
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