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J. Jacob Wikner
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2020 – today
- 2022
- [c36]Yonatan Kifle, J. Jacob Wikner:
A Reconfigurable 13.56MHz Wireless Powered CMOS Integrated Nerve Stimulator. ISCAS 2022: 956-959 - [c35]Oscar Morales Chacon
, J. Jacob Wikner, Atila Alvandpour, Liter Siek
Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters. MIXDES 2022: 93-98 - 2021
- [c34]Oscar Morales Chacon
A digital switching scheme to reduce DAC glitches using code-dependent randomization. NorCAS 2021: 1-5 - 2020
- [c33]Oscar Morales Chacon
A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOS. NorCAS 2020: 1-4
2010 – 2019
- 2019
- [j11]Sohaib A. Qazi
ASIC modelling of SENSE for parallel MRI. Comput. Biol. Medicine 109: 53-61 (2019) - [j10]M. Reza Sadeghifar
Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC. Integr. 66: 128-134 (2019) - [c32]Yonatan Kifle, J. Jacob Wikner, Johan Zötterman, Louise Rydén, Simon Farnebo:
NFC Powered Implantable Temperature Sensor. EMBC 2019: 4359-4362 - 2017
- [c31]Martin Nielsen-Lönn
Self-oscillating multilevel switched-capacitor DC/DC converter for energy harvesting. NORCAS 2017: 1-5 - [c30]Sohaib A. Qazi, Syed Asmat Ali Shah, Hammad Omer, J. Jacob Wikner:
A high-resolution reconfigurable sigma-delta Digital-to-Analog Converter for RF pulse transmission in MRI scanners. NORCAS 2017: 1-6 - 2016
- [j9]Kourosh Hassanli
A low-power wide tuning-range CMOS current-controlled oscillator. Integr. 55: 57-66 (2016) - [j8]Prakash Harikumar, J. Jacob Wikner, Atila Alvandpour:
A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications. IEEE Trans. Circuits Syst. II Express Briefs 63-II(8): 743-747 (2016) - [c29]J. Jacob Wikner, Johan Zötterman, Armin Jalili, Simon Farnebo:
Aiming for the cloud - a study of implanted battery-free temperature sensors using NFC. ISIC 2016: 1-4 - 2015
- [j7]Yinan Wang
Digital estimation and compensation method for nonlinearity mismatches in time-interleaved analog-to-digital converters. Digit. Signal Process. 41: 130-141 (2015) - [j6]Prakash Harikumar, J. Jacob Wikner
A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer. Integr. 50: 28-38 (2015) - [c28]Joakim Alvbrant, Vahid Keshmiri, J. Jacob Wikner
Transfer characteristics and bandwidth limitation in a linear-drift memristor model. ECCTD 2015: 1-4 - [c27]Prakash Harikumar, J. Jacob Wikner
A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications. ECCTD 2015: 1-4 - [c26]Muhammad Irfan Kazim, Muhammad Imran Kazim, J. Jacob Wikner
Complex path impedance estimation and matching requirements for body-coupled communication. ECCTD 2015: 1-4 - [c25]Muhammad Irfan Kazim, Muhammad Imran Kazim, J. Jacob Wikner
Realistic path loss estimation for capacitive body-coupled communication. ECCTD 2015: 1-4 - [c24]Martin Nielsen-Lönn
Design of efficient CMOS rectifiers for integrated piezo-MEMS energy-harvesting power management systems. ECCTD 2015: 1-4 - [c23]Muhammad Touqir Pasha, Yasir Ali Shah
A wide range all-digital delay locked loop for video applications. ECCTD 2015: 1-4 - [c22]Prakash Harikumar, J. Jacob Wikner
Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS. ISCAS 2015: 249-252 - [c21]Prakash Harikumar, J. Jacob Wikner
An ultra-low-voltage OTA in 28 nm UTBB FDSOI CMOS using forward body bias. NORCAS 2015: 1-4 - 2014
- [j5]Nadeem Afzal, J. Jacob Wikner
Reducing Complexity and Power of Digital Multibit Error-Feedback ΔΣ Modulators. IEEE Trans. Circuits Syst. II Express Briefs 61-II(9): 641-645 (2014) - [j4]Pavel Angelov, Syed Ahmed Aamir, J. Jacob Wikner
A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 860-864 (2014) - [j3]Syed Ahmed Aamir, Pavel Angelov, J. Jacob Wikner
1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 888-898 (2014) - [c20]Mohammad Reza Sadeghifar, J. Jacob Wikner
Linear programming design of semi-digital FIR filter and ΣΔ modulator for VDSL2 transmitter. ISCAS 2014: 2465-2468 - [c19]Prakash Harikumar, J. Jacob Wikner
Design of a sampling switch for a 0.4-V SAR ADC using a multi-stage charge pump. NORCHIP 2014: 1-4 - [c18]Martin Nielsen-Lönn
Design considerations for interface circuits to low-voltage piezoelectric energy harvesters. NORCHIP 2014: 1-4 - 2013
- [c17]M. Reza Sadeghifar, Nadeem Afzal, J. Jacob Wikner
A digital-RF converter architecture for IQ modulator with discrete-time low resolution quadrature LO. ICECS 2013: 641-644 - [c16]Syed Ahmed Aamir, Prakash Harikumar, J. Jacob Wikner
Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers. ISCAS 2013: 381-384 - [c15]M. Reza Sadeghifar, J. Jacob Wikner
Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators. ISCAS 2013: 578-581 - 2012
- [c14]Nadeem Afzal, J. Jacob Wikner
Power efficient arrangement of oversampling sigma-delta DAC. NORCHIP 2012: 1-4 - [c13]Joakim Alvbrant, J. Jacob Wikner
Study and simulation of an example redundant FIR filter. NORCHIP 2012: 1-4 - [c12]Prakash Harikumar, Muhammad Irfan Kazim, J. Jacob Wikner
An analog receiver front-end for capacitive body-coupled communication. NORCHIP 2012: 1-4 - 2011
- [j2]Armin Jalili, Sayed Masoud Sayedi, J. Jacob Wikner
A nonlinearity error calibration technique for pipelined ADCs. Integr. 44(3): 229-241 (2011) - [j1]Armin Jalili, Sayed Masoud Sayedi, J. Jacob Wikner
Inter-channel offset and gain mismatch correction for time-interleaved pipelined ADCs. Microelectron. J. 42(1): 158-164 (2011) - [c11]Nadeem Afzal, M. Reza Sadeghifar, J. Jacob Wikner
A study on power consumption of modified noise-shaper architectures for ΣΔ DACs. ECCTD 2011: 274-277 - [c10]Dhurv Chhetri, Venkata Narasimha Manyam
An event-driven 8-bit ADC with a segmented resistor-string DAC. ECCTD 2011: 528-531 - [c9]Prakash Harikumar, Anu Kalidas Muralidharan Pillai, J. Jacob Wikner
A study on switched-capacitor blocks for reconfigurable ADCs. ICECS 2011: 649-652 - [c8]Venkata Narasimha Manyam
Clockless asynchronous delta modulator based ADC for smart dust applications. VLSI-SoC 2011: 331-336 - 2010
- [c7]Syed Ahmed Aamir, J. Jacob Wikner
A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-NM CMOS. ICECS 2010: 29-32 - [c6]Armin Jalili, Sayed Masoud Sayedi, J. Jacob Wikner
Calibration of high-resolution flash ADCS based on histogram test methods. ICECS 2010: 114-117
2000 – 2009
- 2002
- [c5]K. Ola Andersson, Niklas U. Andersson, Mark Vesterbacka, J. Jacob Wikner:
A differential DAC architecture with variable common-mode level. ISCAS (1) 2002: 113-116 - 2001
- [c4]K. Ola Andersson, Niklas U. Andersson, J. Jacob Wikner:
Spectral shaping of DAC nonlinearity errors through modulation of expected errors. ISCAS (3) 2001: 417-420 - [c3]Mark Vesterbacka, J. Jacob Wikner
Design of encoders for linear-coded D/A converters. ISCAS (1) 2001: 524-527 - 2000
- [c2]Mark Vesterbacka, Mikael Rudberg, J. Jacob Wikner
Dynamic element matching in D/A converters with restricted scrambling. ICECS 2000: 36-39 - [c1]Mikael Karlsson Rudberg, Mark Vesterbacka, Niklas U. Andersson, J. Jacob Wikner
Glitch minimization and dynamic element matching in D/A converters. ICECS 2000: 899-902
Coauthor Index
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