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Kwangmin Lim
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2020 – today
- 2024
- [j1]Yong Lim, Jaehoon Lee, Jongmi Lee, Kwangmin Lim, Seunghyun Oh, Jongwoo Lee:
A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm. IEEE J. Solid State Circuits 59(12): 4199-4210 (2024) - [c2]Yong Lim, Jaehoon Lee, Jongmi Lee, Kwangmin Lim, Seunghyun Oh, Jongwoo Lee, Sung-Ung Kwak:
9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm. ISSCC 2024: 170-172 - 2021
- [c1]Yongwoo Lee, Jinsu Yoon, Kwangmin Lim, Bongsik Choi, Geon-Hwi Park, Ju Won Jeon, Jong-Ho Bae, Dong Myong Kim, Dae Hwan Kim, Eunmee Kwon, Sung-Jin Choi:
Vertical and lateral charge losses during short time retention in 3-D NAND flash memory. ESSDERC 2021: 279-282
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last updated on 2024-12-17 20:52 CET by the dblp team
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