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Hsu-Yu Kao
Person information
- affiliation: Chung Yuan Christian University, Taiwan
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2020 – today
- 2022
- [c8]Hsu-Yu Kao, Shih-Hsu Huang:
A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations. AICAS 2022: 166-169 - [c7]Bo-Xi Lai, Shih-Hsu Huang, Hsu-Yu Kao:
A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configuration. ICCE-TW 2022: 141-142 - 2021
- [j2]Hsu-Yu Kao
, Xin-Jia Chen
Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing. Sensors 21(15): 5081 (2021) - [j1]Yui-Kai Weng
Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations. Sensors 21(22): 7468 (2021) - [c6]Yui-Kai Weng, Shih-Hsu Huang, Hsu-Yu Kao:
Block-Based Compression for Reducing Indexing Cost of DNN Accelerators. ICCE-TW 2021: 1-2 - [c5]Wei-Hung Lin, Hsu-Yu Kao, Shih-Hsu Huang:
Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators. ISOCC 2021: 282-283 - 2020
- [c4]Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng:
Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. VTS 2020: 1-6
2010 – 2019
- 2019
- [c3]Fan-Hsuan Tang, Hsu-Yu Kao, Shih-Hsu Huang, Jin-Fu Li:
3D Test Wrapper Chain Optimization with I/O Cells Binding Considered. 3DIC 2019: 1-4 - [c2]Chih-Hsiang Chang, Hsu-Yu Kao, Shih-Hsu Huang:
Hardware Implementation for Multiple Activation Functions. ICCE-TW 2019: 1-2 - [c1]Wei-Hung Lin, Hsu-Yu Kao, Shih-Hsu Huang:
A Design Framework for Hardware Approximation of Deep Neural Networks. ISPACS 2019: 1-2
Coauthor Index
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