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Kishor Kunal
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2020 – today
- 2024
- [c13]Kishor Kunal, Jitesh Poojary, S. Ramprasath
, Ramesh Harjani, Sachin S. Sapatnekar:
Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. ASPDAC 2024: 478-483 - [c12]Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath
Reinforcing the Connection between Analog Design and EDA (Invited Paper). ASPDAC 2024: 665-670 - [i5]Amit Sharma, Teodor-Dumitru Ene, Kishor Kunal, Mingjie Liu, Zafar Hasan, Haoxing Ren:
Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance. CoRR abs/2404.08850 (2024) - 2023
- [j3]Kishor Kunal
GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2801-2814 (2023) - [j2]Sudipta Mondal
A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4844-4857 (2023) - [c11]Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S
Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. ESSDERC 2023: 69-72 - [c10]Sudipta Mondal, Ramprasath S
A Multicore GNN Training Accelerator. ISLPED 2023: 1-6 - [i4]Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Ross Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany, Kishor Kunal, Xiaowei Li, Hao Liu, Stuart F. Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raiman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P. Suthar, Varun Tej, Kaizhe Xu, Haoxing Ren:
ChipNeMo: Domain-Adapted LLMs for Chip Design. CoRR abs/2311.00176 (2023) - 2022
- [c9]Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal
GNNIE: GNN inference engine with load-balancing and graph-specific caching. DAC 2022: 565-570 - 2021
- [j1]Tonmoy Dhar, Kishor Kunal
ALIGN: A System for Automating Analog Layout. IEEE Des. Test 38(2): 8-18 (2021) - [c8]Tonmoy Dhar, Jitesh Poojary
Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. ASP-DAC 2021: 158-163 - [c7]Vidya A. Chhabria
BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology. ICCAD 2021: 1-8 - [c6]Tonmoy Dhar, Kishor Kunal
Machine Learning Techniques in Analog Layout Automation. ISPD 2021: 71-72 - [i3]Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Sachin S. Sapatnekar:
GNNIE: GNN Inference Engine with Load-balancing and Graph-Specific Caching. CoRR abs/2105.10554 (2021) - 2020
- [c5]Kishor Kunal
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE 2020: 55-60 - [c4]Tonmoy Dhar, Kishor Kunal
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD 2020: 54:1-54:2 - [c3]Kishor Kunal, Jitesh Poojary
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. ICCAD 2020: 120:1-120:8 - [c2]Kishor Kunal
Learning from Experience: Applying ML to Analog Circuit Design. ISPD 2020: 55 - [i2]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz:
ALIGN: A System for Automating Analog Layout. CoRR abs/2008.10682 (2020) - [i1]Kishor Kunal
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. CoRR abs/2010.00051 (2020)
2010 – 2019
- 2019
- [c1]Kishor Kunal
ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC 2019: 77
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