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Vighnesh Iyer
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2020 – today
- 2024
- [c6]Kevin Laeufer
, Brandon Fajardo
RTL-Repair: Fast Symbolic Repair of Hardware Design Code. ASPLOS (3) 2024: 867-881 - 2023
- [c5]Kevin Laeufer, Vighnesh Iyer, David Biancolin, Jonathan Bachrach, Borivoje Nikolic, Koushik Sen:
Simulator Independent Coverage for RTL Hardware Languages. ASPLOS (3) 2023: 606-615 - 2022
- [c4]Aditi Deo, Dhrumil Thakore, Riddhi Mistry, Vighnesh Iyer, Prachi Tawde:
A Review of Emotion Detection Systems. IC3I 2022: 32-37 - 2021
- [c3]Hasan Genc, Seah Kim, Alon Amid, Ameer Haj-Ali, Vighnesh Iyer
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration. DAC 2021: 769-774 - [c2]Vighnesh Iyer, Craig B. Zilles:
Pattern Census: A Characterization of Pattern Usage in Early Programming Courses. SIGCSE 2021: 45-51 - 2020
- [j1]John Charles Wright
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2721-2725 (2020)
2010 – 2019
- 2019
- [c1]Vighnesh Iyer
RTL bug localization through LTL specification mining (WIP). MEMOCODE 2019: 5:1-5:5 - [i1]Hasan Genc, Ameer Haj-Ali, Vighnesh Iyer, Alon Amid, Howard Mao, John Charles Wright, Colin Schmidt, Jerry Zhao, Albert J. Ou, Max Banister, Yakun Sophia Shao, Borivoje Nikolic, Ion Stoica, Krste Asanovic:
Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures. CoRR abs/1911.09925 (2019)
Coauthor Index
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last updated on 2024-05-06 20:26 CEST by the dblp team
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