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Shivendra Singh Parihar
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2020 – today
- 2024
- [c6]Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch:
Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction. IRPS 2024: 1-7 - [c5]Benjamin Hien, Marcel Walter, Victor M. van Santen, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch, Robert Wille:
Technology Mapping for Cryogenic CMOS Circuits. ISVLSI 2024: 272-277 - [i1]Shamiul Alam, Simon Thomann, Shivendra Singh Parihar, Yogesh Singh Chauhan, Kai Ni, Hussam Amrouch, Ahmedullah Aziz:
Energy-Efficient Cryogenic Ternary Content Addressable Memory using Ferroelectric SQUID. CoRR abs/2410.11091 (2024) - 2023
- [j2]Shivendra Singh Parihar
, Simon Thomann
Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs. IEEE Open J. Circuits Syst. 4: 258-270 (2023) - [j1]Shivendra Singh Parihar
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K. IEEE Trans. Circuits Syst. I Regul. Pap. 70(8): 3089-3102 (2023) - [c4]Victor M. van Santen, Marcel Walter
Design Automation for Cryogenic CMOS Circuits. DAC 2023: 1-6 - [c3]Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch:
5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing. DRC 2023: 1-2 - 2022
- [c2]Shivendra Singh Parihar, Jun Z. Huang, Weike Wang, Kimihiko Imura, Yogesh Singh Chauhan:
Self-Heating characterization and modeling of 5nm technology node FinFETs. DRC 2022: 1-2
2010 – 2019
- 2019
- [c1]Shivendra Singh Parihar
Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model. VDAT 2019: 667-678
Coauthor Index
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