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Mohamed Ali Jagabar Sathik
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- affiliation: SRM Institute of Science and Technology, Chennai, India
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2020 – today
- 2024
- [j34]M. Jagabar Sathik
:
A Nine Level ANPC Boost Type Inverter Topology With Reduced Component Stress. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 380-384 (2024) - [j33]M. Jagabar Sathik
Improved Dual Boost Mid-Point Clamped Five-Level Inverter Topology. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 3221-3225 (2024) - 2023
- [j32]J. Divya Navamani
Analysis of Higher Dimensional Converter Using Graphical Approach. IEEE Access 11: 75076-75092 (2023) - [j31]M. Jagabar Sathik
A New Boost Topology Seven-Level Inverter of High Voltage Gain Ability and Continuous Input Current With MPPT for PV Grid Integration. IEEE Access 11: 139236-139248 (2023) - [j30]Jagabar Sathik Mohamed Ali
A 7L and 11L High Step-Up SCMLI Topology With Reduced Component Voltage Stress. IEEE Access 11: 139785-139797 (2023) - [j29]Mudadla Dhananjaya, Mohamed Ali Jagabar Sathik
Two-input single-output converter with preserved output voltage under source fault. Int. J. Circuit Theory Appl. 51(11): 5210-5232 (2023) - [j28]Mudadla Dhananjaya
Multi-input multi-output converter for simultaneous buck and boost voltage conversion. Int. J. Circuit Theory Appl. 51(12): 5691-5704 (2023) - [j27]Vishal Anand
Dual Boost Five-Level Switched-Capacitor Inverter With Common Ground. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 556-560 (2023) - 2022
- [j26]Dhafer Al-Makhles
Single Switch Module Type DC-DC Converter With Reduction in Voltage Stress. IEEE Access 10: 107877-107887 (2022) - [j25]Mahmoud F. Elmorshedy
Improved Performance of Hybrid PV and Wind Generating System Connected to the Grid Using Finite-Set Model Predictive Control. IEEE Access 10: 110344-110361 (2022) - 2021
- [j24]Mahajan Sagar Bhaskar
A New Hybrid Zeta-Boost Converter With Active Quad Switched Inductor for High Voltage Gain. IEEE Access 9: 20022-20034 (2021) - [j23]Saeed Alyami
Seven Level T-Type Switched Capacitor Inverter Topology for PV Applications. IEEE Access 9: 85049-85059 (2021) - [j22]J. Divya Navamani
Modified LUO High Gain DC-DC Converter With Minimal Capacitor Stress for Electric Vehicle Application. IEEE Access 9: 122335-122350 (2021) - [j21]Matheswaran Alagu
Performance improvement of solar PV power conversion system through low duty cycle DC-DC converter. Int. J. Circuit Theory Appl. 49(2): 267-282 (2021) - [j20]Rasoul Shalchi Alishah
A new generalized cascade multilevel converter topology and its improved modulation technique. Int. J. Circuit Theory Appl. 49(4): 1103-1120 (2021) - [j19]Suresh Velliangiri
Design of nine step switched capacitor multilevel inverter and its cascaded extension. Int. J. Circuit Theory Appl. 49(4): 1182-1201 (2021) - [j18]Jagabar Sathik Mohamed Ali
Experimental validation of nine-level switched-capacitor inverter topology with high voltage gain. Int. J. Circuit Theory Appl. 49(8): 2479-2493 (2021) - [j17]Rasoul Shalchi Alishah, Kent Bertilsson, Naser Vosoughi Kurdkandi, Seyed Hossein Hosseini, Amirreza Zarrin Gharehkoushan, Jagabar Sathik Mohamed Ali
A New Switched-Ladder Multilevel Converter Structure with Reduced Power Electronic Components. J. Circuits Syst. Comput. 30(12): 2150217:1-2150217:14 (2021) - [j16]M. Jagabar Sathik
Compact Seven-Level Boost Type Inverter Topology. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1358-1362 (2021) - 2020
- [j15]Marif Daula Siddique
A Single DC Source Nine-Level Switched-Capacitor Boost Inverter Topology With Reduced Switch Count. IEEE Access 8: 5840-5851 (2020) - [j14]Dhafer J. Almakhles
An Original Hybrid Multilevel DC-AC Converter Using Single-Double Source Unit for Medium Voltage Applications: Hardware Implementation and Investigation. IEEE Access 8: 71291-71301 (2020) - [j13]Jagabar Sathik Mohamed Ali
A Generalized Multilevel Inverter Topology With Reduction of Total Standing Voltage. IEEE Access 8: 168941-168950 (2020) - [j12]Prem Ponnusamy
A New Multilevel Inverter Topology With Reduced Power Components for Domestic Solar PV Applications. IEEE Access 8: 187483-187497 (2020) - [j11]Atif Iqbal
A New Eight Switch Seven Level Boost Active Neutral Point Clamped (8S-7L-BANPC) Inverter. IEEE Access 8: 203972-203981 (2020) - [j10]M. Jagabar Sathik
A new generalized switched diode multilevel inverter topology with reduced switch count and voltage on switches. Int. J. Circuit Theory Appl. 48(4): 619-637 (2020) - [j9]M. Jagabar Sathik
Improved "K" type seven-level switched capacitor inverter topology with Self-voltage balancing. Int. J. Circuit Theory Appl. 48(10): 1800-1819 (2020) - [j8]M. Jagabar Sathik
An Improved Seven-Level PUC Inverter Topology With Voltage Boosting. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 127-131 (2020) - [j7]Marif Daula Siddique
A New Switched Capacitor 7L Inverter With Triple Voltage Gain and Low Voltage Stress. IEEE Trans. Circuits Syst. II Express Briefs 67-II(7): 1294-1298 (2020) - [j6]M. Jagabar Sathik
High Gain Active Neutral Point Clamped Seven-Level Self-Voltage Balancing Inverter. IEEE Trans. Circuits Syst. 67-II(11): 2567-2571 (2020) - [j5]Marif Daula Siddique
Reduced Switch Count Based Single Source 7L Boost Inverter Topology. IEEE Trans. Circuits Syst. 67-II(12): 3252-3256 (2020) - [j4]M. Jagabar Sathik
Cross Connected Compact Switched-Capacitor Multilevel Inverter (C3-SCMLI) Topology With Reduced Switch Count. IEEE Trans. Circuits Syst. 67-II(12): 3287-3291 (2020)
2010 – 2019
- 2019
- [j3]Marif Daula Siddique
A New Single Phase Single Switched-Capacitor Based Nine-Level Boost Inverter Topology With Reduced Switch Count and Voltage Stress. IEEE Access 7: 174178-174188 (2019) - [j2]S. A. Ahamed Ibrahim
A New Asymmetric and Cascaded Switched Diode Multilevel Inverter Topology for Reduced Switches, DC Source and Blocked Voltage on Switches. J. Circuits Syst. Comput. 28(4): 1950064:1-1950064:30 (2019) - [c1]M. Jagabar Sathik
A New 5-Level ANPC Switched Capacitor Inverter Topology for Photovoltaic Applications. IECON 2019: 3487-3492 - 2018
- [j1]Palanisamy Ramasamy
Three-Dimensional Space Vector Modulation Strategy for Capacitor Balancing in Split Inductor Neutral-Point Clamped Multilevel Inverters. J. Circuits Syst. Comput. 27(14): 1850232:1-1850232:20 (2018)
Coauthor Index
aka: Dhafer J. Almakhles
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last updated on 2024-08-05 20:20 CEST by the dblp team
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