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Masataka Matsui
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2000 – 2009
- 2007
- [j7]Shen Li, Lingfeng Li, Takeshi Ikenaga, Shunichi Ishiwata, Masataka Matsui, Satoshi Goto:
Content-Based Complexity Reduction Methods for MPEG-2 to H.264 Transcoding. IEICE Trans. Inf. Syst. 90-D(1): 90-98 (2007) - 2006
- [j6]Shen Li, Takeshi Ikenaga, Hideki Takeda, Masataka Matsui, Satoshi Goto:
A Hardware Implementation of a Content-Based Motion Estimation Algorithm for Real-Time MPEG-4 Video Coding. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 932-940 (2006) - [c7]Shen Li, Lingfeng Li, Takeshi Ikenaga, Shunichi Ishiwata, Masataka Matsui, Satoshi Goto:
Complexity Based Fast Coding Mode Decision for MPEG-2 / H.264 Video Transcoding. APCCAS 2006: 574-577 - 2005
- [j5]Takashi Miyamori, Jun Tanabe, Yasuhiro Taniguchi, Kenji Furukawa, Tatsuo Kozakaya, Hiroaki Nakai, Yukimasa Miyamoto, Ken-ichi Maeda, Masataka Matsui:
Development of Image Recognition Processor Based on Configurable Processor. J. Robotics Mechatronics 17(4): 437-446 (2005) - [c6]Lawrence Clark, Masataka Matsui:
DSP for wireless. CICC 2005: 66-67 - 2003
- [j4]Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Mitsuo Saito, Takashi Miyamori, Goichi Ootomo, Masataka Matsui:
A single-chip MPEG-2 codec based on customizable media embedded processor. IEEE J. Solid State Circuits 38(3): 530-540 (2003) - [c5]Jun Tanahe, Yasuhiro Taniguchi, Takashi Miyamori, Yukimasa Miyamoto, Hideki Takeda, Masaya Tarui, Hiromitsu Nakayama, Nohuyulu Takeda, Kenichi Maeda
, Masataka Matsui:
Visconti: multi-VLIW image recognition processor based on configurable processor [obstacle detection applications]. CICC 2003: 185-188 - 2002
- [c4]Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Takashi Miyamori, Goichi Ootomo, Masataka Matsui:
A single-chip MPEG-2 codec based on customizable media microprocessor. CICC 2002: 163-166 - [c3]Atsushi Mizuno, Kazuyoshi Kohno, Ryuichiro Ohyama, Takahiro Tokuyoshi, Hironori Uetani, Hans Eichel, Takashi Miyamori, Nobu Matsumoto, Masataka Matsui:
Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture. ICCD 2002: 2-7 - 2000
- [c2]Norman Kojima, Yukiko Parameswar, Christian Klingner, Yukio Ohtaguro, Masataka Matsui, Shigeaki Iwasa, Tatsuo Teruyama, Takayoshi Shimazawa, Hideki Takeda, Kouji Hashizume, Haruyuki Tago, Masaaki Yamada:
Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor. ASP-DAC 2000: 641-646 - [c1]Vjekoslav Svilan, Masataka Matsui, James B. Burr:
Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS. ISLPED 2000: 268-272
1990 – 1999
- 1994
- [j3]Yasuo Unekawa, Tsuguo Kobayashi, Tsukasa Shirotori, Yukihiro Fujimoto, Takayoshi Shimazawa, Kazutaka Nogami, Takehiko Nakao, Kazukiro Sawada, Masataka Matsui, Takayasu Sakurai, Man Kit Tang, William A. Huffman:
A 110-MHz/1-Mb synchronous TagRAM. IEEE J. Solid State Circuits 29(4): 403-410 (1994) - [j2]Masataka Matsui, Hiroyuki Hara, Yoshiharu Uetani, Lee-Sup Kim, Tetsu Nagamatsu, Yoshinori Watanabe, Akihiko Chiba, Kouji Matsuda, Takayasu Sakurai:
A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme. IEEE J. Solid State Circuits 29(12): 1482-1490 (1994)
1980 – 1989
- 1989
- [j1]Masataka Matsui, Hiroshi Momose, Yukihiro Urakawa, Takeo Maeda, Azuma Suzuki, Nobuaki Urakawa, Katsuhiko Sato, Jun'ichi Matsunaga, Kiyofumi Ochii:
An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters. IEEE J. Solid State Circuits 24(5): 1226-1232 (1989)
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