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Francesco Minervini
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2020 – today
- 2024
- [j3]Marcello Barbirotta
, Francesco Minervini
Enhancing Fault Tolerance in High-Performance Computing: A Real Hardware Case Study on a RISC-V Vector Processing Unit. IEEE Open J. Comput. Soc. 5: 553-565 (2024) - 2023
- [j2]Mate Kovac
FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit. Microprocess. Microsystems 97: 104762 (2023) - [j1]Francesco Minervini
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications. ACM Trans. Archit. Code Optim. 20(2): 28:1-28:25 (2023) - [c3]Lluc Alvarez
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. CF 2023: 309-314 - 2022
- [c2]Guillem Cabo, Gerard Candón, Xavier Carril
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. DCIS 2022: 1-6
2010 – 2019
- 2018
- [c1]Pasquale Davide Schiavone, Ernesto Sánchez, Annachiara Ruospo
An Open-Source Verification Framework for Open-Source Cores: A RISC-V Case Study. VLSI-SoC 2018: 43-48
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last updated on 2024-10-23 20:29 CEST by the dblp team
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