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Yun-Chen Lo
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2020 – today
- 2024
- [j3]Hung-Hsi Hsu
, Tai-Hao Wen, Wei-Hsing Huang, Win-San Khwa, Yun-Chen Lo
A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme. IEEE J. Solid State Circuits 59(1): 116-127 (2024) - [j2]Yun-Chen Lo
ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory. IEEE Trans. Computers 73(9): 2136-2149 (2024) - 2023
- [j1]Yun-Chen Lo
LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks. IEEE Comput. Archit. Lett. 22(2): 125-128 (2023) - [c13]Yun-Chen Lo, Ren-Shuo Liu:
Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference. DAC 2023: 1-6 - [c12]Yun-Chen Lo, Ren-Shuo Liu:
Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture. DAC 2023: 1-6 - [c11]Chia-Chun Wang
Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators. ICCD 2023: 515-522 - [c10]Yun-Chen Lo, Chia-Chun Wang, Ren-Shuo Liu:
BICEP: Exploiting Bitline Inversion for Efficient Operation-Unit-Based Compute-in-Memory Architecture: No Retraining Needed! ICCD 2023: 531-534 - [c9]Yun-Chen Lo, Tse-Kuang Lee, Ren-Shuo Liu:
Block and Subword-Scaling Floating-Point (BSFP) : An Efficient Non-Uniform Quantization For Low Precision Inference. ICLR 2023 - [c8]Wei-Hsing Huang, Tai-Hao Wen, Je-Min Hung, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Hung-Hsi Hsu, Yu-Hsiang Chin, Yu-Chiao Chen, Chuna-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W. ISSCC 2023: 258-259 - [c7]Yun-Chen Lo
Bucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs. MICRO 2023: 1002-1015 - 2022
- [c6]Yun-Chen Lo, Chih-Chen Yeh, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Wen-Chien Ting, Ren-Shuo Liu:
ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators. ICCAD 2022: 86:1-86:9 - 2021
- [c5]Yun-Chen Lo, Bing Li, Sooyong Park, Kwanwoo Shin
Interference-Free Design Methodology for Paper-Based Digital Microfluidic Biochips. ASP-DAC 2021: 79-84 - 2020
- [c4]Cheng-Xin Xue, Tsung-Yuan Huang, Je-Syu Liu, Ting-Wei Chang, Hui-Yao Kao, Jing-Hong Wang, Ta-Wei Liu, Shih-Ying Wei, Sheng-Po Huang, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen, Yun-Chen Lo, Tai-Hsing Wen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices. ISSCC 2020: 244-246 - [c3]Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su
15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. ISSCC 2020: 246-248
2010 – 2019
- 2019
- [c2]Yun-Chen Lo, Yu-Chun Kuo, Yun-Sheng Chang, Jian-Hao Huang, Jun-Shen Wu, Wen-Chien Ting, Tai-Hsing Wen, Ren-Shuo Liu:
Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN). ESSCIRC 2019: 241-244 - 2018
- [c1]Ren-Shuo Liu, Yun-Chen Lo, Yuan-Chun Luo, Chih-Yu Shen, Cheng-Ju Lee:
DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout. VLSI-DAT 2018: 1-4
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