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Stefania Perri
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- affiliation: University of Calabria, Arcavacata di Rende, Italy
- affiliation (PhD 2000): University of Reggio Calabria, Italy
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2020 – today
- 2024
- [j61]Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
Efficient implementation of signed multipliers on FPGAs. Comput. Electr. Eng. 116: 109217 (2024) - [j60]Cosimo Ieracitano
, Nadia Mammone
An explainable embedded neural system for on-board ship detection from optical satellite imagery. Eng. Appl. Artif. Intell. 133: 108517 (2024) - [j59]Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
Approximate bilateral filters for real-time and low-energy imaging applications on FPGAs. J. Supercomput. 80(11): 15894-15916 (2024) - [j58]Fanny Spagnolo
Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1472-1484 (2024) - [c41]Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
KIT: Kernel Isotropic Transformation of Bilateral Filters for Image Denoising on FPGA. FPL 2024: 19-23 - [c40]Stefania Perri:
RAW 2024 Invited Talk-2: Digital In-Memory Computing to Accelerate Deep Learning Inference on the Edge. IPDPS (Workshops) 2024: 84 - [c39]Stefania Perri, Cristian Zambelli, Daniele Ielmini, Cristina Silvano:
Digital In-Memory Computing to Accelerate Deep Learning Inference on the Edge. IPDPS (Workshops) 2024: 130-133 - 2023
- [j57]Fanny Spagnolo
Design of Approximate Bilateral Filters for Image Denoising on FPGAs. IEEE Access 11: 1990-2000 (2023) - [j56]Stefania Perri
Design of Leading Zero Counters on FPGAs. IEEE Embed. Syst. Lett. 15(3): 149-152 (2023) - [j55]Fabio Frustaci
A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 756-760 (2023) - [j54]Cristian Sestito
FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis. J. Signal Process. Syst. 95(10): 1245-1263 (2023) - [i2]Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. CoRR abs/2306.15552 (2023) - [i1]Fabrizio Ferrandi
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures. CoRR abs/2311.17815 (2023) - 2022
- [j53]Fanny Spagnolo
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems. IEEE Access 10: 7073-7081 (2022) - [j52]Fabio Frustaci, Fanny Spagnolo
Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes. Sensors 22(8): 2839 (2022) - [j51]Fanny Spagnolo
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1652-1656 (2022) - [j50]Stefania Perri
Multibit Full Comparator Logic in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4508-4512 (2022) - [c38]Cristian Sestito
Design-Space Exploration of Quantized Transposed Convolutional Neural Networks for FPGA-based Systems-on-Chip. DASC/PiCom/CBDCom/CyberSciTech 2022: 1-6 - [c37]Cristian Sestito
Accuracy Evaluation of Transposed Convolution-Based Quantized Neural Networks. IJCNN 2022: 1-8 - [c36]Emanuel Marrazzo, Fanny Spagnolo, Stefania Perri:
Runtime Reconfigurable Hardware Accelerator for Energy-Efficient Transposed Convolutions. PRIME 2022: 141-144 - 2021
- [j49]Cristian Sestito
Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions. J. Imaging 7(10): 210 (2021) - [j48]Stefania Perri
Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA. IEEE Trans. Circuits Syst. II Express Briefs 68(11): 3456-3460 (2021) - 2020
- [j47]Stefania Perri
Parallel architecture of power-of-two multipliers for FPGAs. IET Circuits Devices Syst. 14(3): 381-389 (2020) - [j46]Fanny Spagnolo
Design of a real-time face detection architecture for heterogeneous systems-on-chips. Integr. 74: 1-10 (2020) - [j45]Stefania Perri
Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip. J. Imaging 6(9): 85 (2020) - [j44]Stefania Perri
Stereo vision architecture for heterogeneous systems-on-chip. J. Real Time Image Process. 17(2): 393-415 (2020) - [j43]Fabio Frustaci
Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation. IEEE Trans. Circuits Syst. 67-II(12): 3427-3431 (2020) - [c35]Cristian Sestito
An Efficient Convolution Engine based on the À-trous Spatial Pyramid Pooling. ASAP 2020: 77-80 - [c34]Fanny Spagnolo
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs. ICECS 2020: 1-4 - [c33]Fanny Spagnolo
Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip. MECO 2020: 1-5
2010 – 2019
- 2019
- [j42]Giuseppe Cocorullo
Multimodal background subtraction for high-performance embedded systems. J. Real Time Image Process. 16(5): 1407-1423 (2019) - [j41]Fanny Spagnolo
An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis. Sensors 19(14): 3055 (2019) - [j40]Fabio Frustaci
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 964-968 (2019) - [c32]Fanny Spagnolo
Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs. PRIME 2019: 229-232 - 2018
- [c31]Fanny Spagnolo
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems. ICECS 2018: 749-752 - [c30]Fanny Spagnolo
Designing Fast Convolutional Engines for Deep Learning Applications. ICECS 2018: 753-756 - [c29]Stefania Perri
Design of Real-Time FPGA-based Embedded System for Stereo Vision. ISCAS 2018: 1-5 - 2017
- [j39]Giuseppe Cocorullo
Design of Efficient BCD Adders in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs 64-II(5): 575-579 (2017) - 2016
- [j38]Giuseppe Cocorullo
Design of efficient QCA multiplexers. Int. J. Circuit Theory Appl. 44(3): 602-615 (2016) - [j37]Giuseppe Cocorullo
An efficient hardware-oriented stereo matching algorithm. Microprocess. Microsystems 46: 21-33 (2016) - 2015
- [j36]Pasquale Corsonello
Power supply noise in accurate delay model for the sub-threshold domain. Integr. 50: 127-136 (2015) - [j35]Marco Lanuzza
Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 388-391 (2015) - [j34]Pasquale Corsonello
Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 3133-3137 (2015) - [c28]Pasquale Corsonello
Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology. ICCD 2015: 499-504 - 2014
- [j33]Pasquale Corsonello
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates. Int. J. Circuit Theory Appl. 42(1): 65-70 (2014) - [j32]Fabio Frustaci
Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. Int. J. Circuit Theory Appl. 42(5): 452-467 (2014) - [j31]Stefania Perri
Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. Int. J. Circuit Theory Appl. 42(7): 731-743 (2014) - [j30]Pasquale Corsonello
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1456-1464 (2014) - [j29]Stefania Perri
Area-Delay Efficient Binary Adders in QCA. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1174-1179 (2014) - [c27]Lorena Guachi
A novel background subtraction method based on color invariants and grayscale levels. ICCST 2014: 1-5 - 2013
- [j28]Stefania Perri
Adaptive Census Transform: A novel hardware-oriented stereovision algorithm. Comput. Vis. Image Underst. 117(1): 29-41 (2013) - 2012
- [j27]Fabio Frustaci
Energy-efficient single-clock-cycle binary comparator. Int. J. Circuit Theory Appl. 40(3): 237-246 (2012) - [j26]Paolo Zicari
Low-cost FPGA stereo vision system for real time disparity maps calculation. Microprocess. Microsystems 36(4): 281-288 (2012) - [j25]Marco Lanuzza
Comparative analysis of yield optimized pulsed flip-flops. Microelectron. Reliab. 52(8): 1679-1689 (2012) - [j24]Fabio Frustaci
Analytical Delay Model Considering Variability Effects in Subthreshold Domain. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 168-172 (2012) - [j23]Marco Lanuzza
Low-Power Level Shifter for Multi-Supply Voltage Designs. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 922-926 (2012) - 2011
- [j22]Stefania Perri
Efficient memory architecture for image processing. Int. J. Circuit Theory Appl. 39(3): 351-356 (2011) - [j21]Stefania Perri
Fast-squarer circuits using 3-bit-scan without overlapping bits. Int. J. Circuit Theory Appl. 39(10): 1037-1047 (2011) - 2010
- [j20]Marco Lanuzza
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. ACM Trans. Reconfigurable Technol. Syst. 4(1): 8:1-8:22 (2010) - [c26]Fabio Frustaci
A new low-power high-speed single-clock-cycle binary comparator. ISCAS 2010: 317-320 - [c25]Marco Lanuzza
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. ISVLSI 2010: 458-459 - [c24]Marco Lanuzza
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. PATMOS 2010: 180-189
2000 – 2009
- 2009
- [j19]Fabio Frustaci
Low-power split-path data-driven dynamic logic. IET Circuits Devices Syst. 3(6): 303-312 (2009) - [j18]Sohan Purohit, Marco Lanuzza
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. J. Low Power Electron. 5(3): 326-338 (2009) - [j17]Fabio Frustaci
Designing High-Speed Adders in Power-Constrained Environments. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 172-176 (2009) - [c23]Marco Lanuzza
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. ARC 2009: 74-84 - [c22]Sohan Purohit, Marco Lanuzza
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design 2009: 45-50 - 2008
- [j16]Fabio Frustaci
High-performance noise-tolerant circuit techniques for CMOS dynamic logic. IET Circuits Devices Syst. 2(6): 537-548 (2008) - [j15]Paolo Zicari
A matrix product accelerator for field programmable systems on chip. Microprocess. Microsystems 32(2): 53-67 (2008) - [j14]Paolo Zicari
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals. Microprocess. Microsystems 32(8): 437-446 (2008) - [j13]Stefania Perri
Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator. IEEE Trans. Circuits Syst. II Express Briefs 55-II(12): 1239-1243 (2008) - [c21]Fabio Frustaci
A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. PATMOS 2008: 277-286 - [c20]Marco Lanuzza
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. PATMOS 2008: 297-306 - 2007
- [j12]Stefania Perri
VLSI implementations of efficient isotropic flexible 2D convolvers. IET Circuits Devices Syst. 1(4): 263-269 (2007) - [c19]Marco Lanuzza
A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. AHS 2007: 119-126 - [c18]Emanuele Sciagura, Paolo Zicari
An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector. DSD 2007: 102-108 - [c17]Pasquale Corsonello
Design and Implementation of a 90nm Low bit-rate Image Compression Core. DSD 2007: 383-389 - [c16]Marco Lanuzza
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. SAMOS 2007: 159-168 - 2006
- [j11]Stefania Perri
Simd Multipliers for Accelerating Embedded Processors in FPGAS. J. Circuits Syst. Comput. 15(4): 537-550 (2006) - [j10]Pasquale Corsonello
Low bit rate image compression core for onboard space applications. IEEE Trans. Circuits Syst. Video Technol. 16(1): 114-128 (2006) - [j9]Fabio Frustaci
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1238-1249 (2006) - [c15]Paolo Zicari, Pasquale Corsonello
An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs. ICECS 2006: 168-171 - [c14]Stefania Perri
SAD-Based Stereo Matching Circuit for FPGAs. ICECS 2006: 846-849 - [c13]Pasquale Corsonello, Stefania Perri, Martin Margala:
An integrated countermeasure against differential power analysis for secure smart-cards. ISCAS 2006 - [c12]Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
Leakage energy reduction techniques in deep submicron cache memories: a comparative study. ISCAS 2006 - 2005
- [j8]Pasquale Corsonello
Efficient Reconfigurable Manchester Adders for Low-power Media Processing. J. Circuits Syst. Comput. 14(1): 57-64 (2005) - [j7]Pasquale Corsonello
Microprocessor-based FPGA implementation of SPIHT image compression subsystems. Microprocess. Microsystems 29(6): 299-305 (2005) - [j6]Stefania Perri
A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocess. Microsystems 29(8-9): 381-391 (2005) - [j5]Pasquale Corsonello
Efficient Addition Circuits for Modular Design of Processors-in-Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(8): 1557-1567 (2005) - [c11]Marco Lanuzza
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. FPL 2005: 13-18 - [c10]Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
Fast Low-Power 64-Bit Modular Hybrid Adder. PATMOS 2005: 609-617 - 2004
- [j4]Stefania Perri
Variable precision arithmetic circuits for FPGA-based multimedia processors. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 995-999 (2004) - [c9]Pasquale Corsonello, Stefania Perri, Vitit Kantabutra:
Area- and Power-Reduced Standard-Cell Spanning Tree Adders. ESA/VLSI 2004: 343-352 - 2003
- [j3]Stefania Perri
A high-speed energy-efficient 64-bit reconfigurable binary adder. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 939-943 (2003) - [c8]Pasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe Cocorullo:
Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems. FPL 2003: 661-669 - [c7]Stefania Perri
A low-power sub-nanosecond standard-cells based adder. ICECS 2003: 296-299 - 2002
- [j2]Stefania Perri
VLSI circuits for low-power high-speed asynchronous addition. IEEE Trans. Very Large Scale Integr. Syst. 10(5): 608-613 (2002) - [c6]Stefania Perri
Speed-efficient wide adders for VIRTEX FPGAs. ICECS 2002: 599-602 - 2001
- [c5]Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, Gregorio Cappuccino, Giovanni Staino:
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits. ICECS 2001: 723-727 - [c4]Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo, Stefania Perri, Giovanni Staino:
Dynamic power of CMOS gates driving lossy transmission lines. ICECS 2001: 1579-1582 - 2000
- [j1]Pasquale Corsonello
Area-time-power tradeoff in cellular arrays VLSI implementations. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 614-624 (2000) - [c3]Stefania Perri
Designing High-Speed Asynchronous Pipelines. EUROMICRO 2000: 1394-1399 - [c2]Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. PATMOS 2000: 195-204
1990 – 1999
- 1999
- [c1]Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
A 56-bit self-timed adder for high speed asynchronous datapath. ICECS 1999: 37-41
Coauthor Index
[j61] [j60] [j59] [j58] [c41] [j57] [j56] [j55] [j53] [j52] [j51] [j50] [j48] [j47] [j46] [j45] [j44] [j43] [c35] [c34] [c33] [j42] [j41] [j40] [c32] [c31] [c30] [c29] [j39] [j38] [j37] [j36] [j35] [j34] [c28] [j33] [j32] [j31] [j30] [j29] [c27] [j28] [j27] [j26] [j25] [j24] [j23] [j22] [j21] [j20] [c26] [c25] [c24] [j19] [j18] [j17] [c23] [c22] [j16] [j15] [j14] [j13] [c21] [c20] [j12] [c19] [c18] [c17] [c16] [j11] [j10] [j9] [c15] [c14] [c13] [c12] [j8] [j7] [j6] [j5] [c11] [c10] [j4] [c9] [j3] [c8] [c7] [j2] [c6] [c5] [c4] [j1] [c3] [c2] [c1]
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last updated on 2024-12-10 20:41 CET by the dblp team
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