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Yuanyong Luo
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2020 – today
- 2024
- [j14]Yu Wang
, Xingcheng Liang, Shuai Niu
FDM: Fused Double-Multiply Design for Low-Latency and Area- and Power-Efficient Implementation. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 450-454 (2024) - [c5]Yu Wang, Haoyu Zhang, Wei Hu, Xin Zhang, Xinyu Tian, Fei Lyu
An Optimized Architecture for Computing the Square Root of Complex Numbers. ISCAS 2024: 1-5 - [i1]Yuanyong Luo, Zhongxing Zhang, Richard Wu, Hu Liu, Ying Jin, Kai Zheng, Minmin Wang, Zhanying He, Guipeng Hu, Luyao Chen, Tianchi Hu, Junsong Wang, Minqi Chen, Mikhaylov Dmitry, Korviakov Vladimir, Bobrin Maxim, Yuhao Hu, Guanfu Chen, Zeyi Huang:
Ascend HiFloat8 Format for Deep Learning. CoRR abs/2409.16626 (2024) - 2022
- [j13]Fei Lyu, Chaoran Wu, Yuxuan Wang, Hongbing Pan, Yu Wang, Yuanyong Luo
An optimized hardware implementation of the CORDIC algorithm. IEICE Electron. Express 19(21): 20220362 (2022) - [j12]Fei Lyu
ML-PLAC: Multiplierless Piecewise Linear Approximation for Nonlinear Function Evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1546-1559 (2022) - [j11]Fei Lyu
High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers. IEEE Trans. Very Large Scale Integr. Syst. 30(4): 544-548 (2022) - [c4]Fei Lyu, Jian Chen, Shuo Huang, Wenxiu Wang, Yuanyong Luo
Reconfigurable Multifunction Computing Unit Using an Universal Piecewise Linear Method. ISCAS 2022: 2117-2121 - 2021
- [j10]Xuan Chen, Xiaopeng Yuan, Gaoming Fu
Effective Plug-Ins for Reducing Inference-Latency of Spiking Convolutional Neural Networks During Inference Phase. Frontiers Comput. Neurosci. 15: 697469 (2021) - [j9]Fei Lyu
Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 715-727 (2021) - [j8]Fei Lyu
PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1470-1474 (2021) - [j7]Muhan Zheng
CLA Formula and its Acceleration of Architecture Design for Clustered Look-Ahead Pipelined Recursive Digital Filter. J. Signal Process. Syst. 93(6): 617-629 (2021) - 2020
- [j6]Huaqing Sun
A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 177-188 (2020) - [j5]Yuxuan Wang
GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 864-875 (2020) - [j4]Hongxi Dong
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 2014-2027 (2020) - [c3]Hui Chen, Lin Jiang, Yuanyong Luo
A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions. ISCAS 2020: 1-5 - [c2]Manzhen Wang, Yuanyong Luo
An Optimized Compression Strategy for Compressor-Based Approximate Multiplier. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j3]Yuanyong Luo
Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2156-2169 (2019) - [j2]Yuanyong Luo
Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base". IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2222 (2019) - [c1]Yuanyong Luo
CLA Formula Aided Fast Architecture Design for Clustered Look-Ahead Pipelined IIR Digital Filter. SiPS 2019: 60-66 - 2018
- [j1]Yuanyong Luo
CORDIC-Based Architecture for Computing Nth Root and Its Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4183-4195 (2018)
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